Datasheet

ADS7843
10
SBAS090B
www.ti.com
FIGURE 8. Ideal Input Voltages and Output Codes.
Output Code
0V
FS = Full-Scale Voltage = V
REF
(1)
1LSB = V
REF
(1)
/4096
FS – 1LSB
11...111
11...110
11...101
00...010
00...001
00...000
1LSB
NOTES: (1) Reference voltage at converter: +REF – (–REF). See Figure 2.
(2) Input voltage at converter, after multiplexer: +IN – (–IN). See Figure 2
Input Voltage
(2)
(V)
This is possible provided that each conversion completes
within 1.6ms of starting. Otherwise, the signal that has been
captured on the input sample-and-hold may droop enough to
affect the conversion result. Note that the ADS7843 is fully
powered while other serial communications are taking place
during a conversion.
Digital Timing
Figure 7 and Table VI provide detailed timing for the digital
interface of the ADS7843.
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
ACQ
Acquisition Time 1.5 µs
t
DS
DIN Valid Prior to DCLK Rising 100 ns
t
DH
DIN Hold After DCLK HIGH 10 ns
t
DO
DCLK Falling to DOUT Valid 200 ns
t
DV
CS Falling to DOUT Enabled 200 ns
t
TR
CS Rising to DOUT Disabled 200 ns
t
CSS
CS Falling to First DCLK Rising 100 ns
t
CSH
CS Rising to DCLK Ignored 0 ns
t
CH
DCLK HIGH 200 ns
t
CL
DCLK LOW 200 ns
t
BD
DCLK Falling to BUSY Rising 200 ns
t
BDV
CS Falling to BUSY Enabled 200 ns
t
BTR
CS Rising to BUSY Disabled 200 ns
TABLE VI. Timing Specifications (+V
CC
= +2.7V and Above,
T
A
= –40°C to +85°C, C
LOAD
= 50pF).
FIGURE 7. Detailed Timing Diagram.
PD0
t
BDV
t
DH
t
CH
t
CL
t
DS
t
CSS
t
DV
t
BD
t
BD
t
TR
t
BTR
t
D0
t
CSH
DCLK
CS
11 DOUT
BUSY
DIN
10
Data Format
The ADS7843 output data is in Straight Binary format, as
shown in Figure 8. This figure shows the ideal output code for
the given input voltage and does not include the effects of
offset, gain, or noise.
8-Bit Conversion
The ADS7843 provides an 8-bit conversion mode that can be
used when faster throughput is needed and the digital result
is not as critical. By switching to the 8-bit mode, a conversion
is complete four clock cycles earlier. This could be used in
conjunction with serial interfaces that provide 12-bit transfers
or two conversions could be accomplished with three 8-bit
transfers. Not only does this shorten each conversion by four
bits (25% faster throughput), but each conversion can actu-
ally occur at a faster clock rate. This is because the internal
settling time of the ADS7843 is not as critical—settling to
better than 8 bits is all that is needed. The clock rate can be
as much as 50% faster. The faster clock rate and fewer clock
cycles combine to provide a 2x increase in conversion rate.