Datasheet

ADS7842
SBAS103C
13
www.ti.com
REFERENCE INPUT
The external reference sets the analog input range. The
ADS7842 will operate with a reference in the range of 100mV
to +V
CC
.
There are several critical items concerning the reference
input and its wide voltage range. As the reference voltage is
reduced, the analog voltage weight of each digital output
code is also reduced. This is often referred to as the LSB size
and is equal to the reference voltage divided by 4096. Any
offset or gain error inherent in the ADC will appear to
increase, in terms of LSB size, as the reference voltage is
reduced. For example, if the offset of a given converter is
2LSBs with a 2.5V reference, then it will typically be 10LSBs
with a 0.5V reference. In each case, the actual offset of the
device is the same, 1.22mV.
Likewise, the noise or uncertainty of the digitized output will
increase with lower LSB size. With a reference voltage of
100mV, the LSB size is 24µV. This level is below the internal
noise of the device. As a result, the digital output code will not
be stable and vary around a mean value by a number of
LSBs. The distribution of output codes will be gaussian and
the noise can be reduced by simply averaging consecutive
conversion results or applying a digital filter.
With a lower reference voltage, care should be taken to
provide a clean layout including adequate bypassing, a clean
(low-noise, low-ripple) power supply, a low-noise reference,
and a low-noise input signal. Because the LSB size is lower,
the converter will also be more sensitive to nearby digital
signals and electromagnetic interference.
The voltage into the V
REF
input is not buffered and directly
drives the CDAC portion of the ADS7842. Typically, the input
current is 13µA with a 2.5V reference. This value will vary by
microamps depending on the result of the conversion. The
reference current diminishes directly with both conversion
rate and reference voltage. As the current from the reference
is drawn on each bit decision, clocking the converter more
quickly during a given conversion period will not reduce
overall current drain from the reference.
Data Format
The ADS7842 output data is in Straight Offset Binary format,
see Table IV. This table shows the ideal output code for the
given input voltage and does not include the effects of offset,
gain, or noise.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS7842 circuitry. This is particularly
true if the reference voltage is low and/or the conversion rate
is high.
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connec-
tions, and digital inputs that occur just prior to latching the
output of the analog comparator. Thus, during any single
conversion for an n-bit SAR converter, there are n “windows”
in which large external transient voltages can easily affect the
conversion result. Such glitches might originate from switch-
ing power supplies, nearby digital logic, and high-power
devices. The degree of error in the digital output depends on
the reference voltage, layout, and the exact timing of the
external event. The error can change if the external event
changes in time with respect to the DCLK input.
With this in mind, power to the ADS7842 should be clean and
well bypassed. A 0.1µF ceramic bypass capacitor should be
placed as close to the device as possible. In addition, a 1µF
to 10µF capacitor and a 5Ω or 10Ω series resistor may be
used to low-pass filter a noisy supply.
The reference should be similarly bypassed with a 0.1µF
capacitor. Again, a series resistor and large capacitor can be
used to low-pass filter the reference voltage. If the reference
voltage originates from an op amp, make sure that it can
drive the bypass capacitor without oscillation (the series
resistor can help in this case). The ADS7842 draws very little
current from the reference on average, but it does place
larger demands on the reference circuitry over short periods
of time (on each rising edge of CLK during a conversion).
The ADS7842 architecture offers no inherent rejection of
noise or voltage variation in regards to the reference input.
This is of particular concern when the reference input is tied
to the power supply. Any noise and ripple from the supply will
appear directly in the digital results. While high frequency
noise can be filtered out as discussed in the previous
paragraph, voltage variation due to line frequency (50Hz or
60Hz) can be difficult to remove.
The GND pin should be connected to a clean ground point. In
many cases, this will be the “analog” ground. Avoid connec-
tions which are too near the grounding point of a microcontroller
or digital signal processor. If needed, run a ground trace
directly from the converter to the power-supply entry point. The
ideal layout will include an analog ground plane dedicated to
the converter and associated analog circuitry.