Datasheet

ADS7842
SBAS103C
12
www.ti.com
FIGURE 4. Read Timing Following a Conversion.
FIGURE 5. Entering Power-Down Using RD and A0.
FIGURE 6. Initiating Wake-Up Using RD and A0.
t
1
t
12
t
11
t
14
t
13
t
3
NOTE: Internal register of current conversion updated 1/2 clock cycle prior to BUSY going HIGH.
CS
RD
CLK
BUSY
n – 1
Conversion n
To prevent PWD
A0 must be 0
n-1 DATA VALID
A0
DB0-DB11
t
3
t
16
t
15
t
1
t
12
t
11
t
2
CS
RD
CLK
BUSY
A0
NOTE: Rising edge of RD while A0 = 1 initiates power down immediately.
CS
RD
A0
t
1
t
2
t
15
t
16
t
3
NOTE: Rising edge of 2nd RD while A0 = 0 places the ADS7842 in sample mode.