Datasheet

10ADS7835
®
D11
(MSB)
DATA
HOLD SAMPLESAMPLE HOLD
CLK
CONV
SAMPLE/HOLD
MODE
POWER MODE FULL POWER FULL POWERLOW POWER
D10 D1
D0
(LSB)
t
CKPD
t
CVPU
t
CVSP
123 1213
t
ACQ
CONVERSION IN PROGRESS IDLE IDLE
INTERNAL
CONVERSION
STAT E
NOTES: (1) The low power mode (“power-down”) is entered when CONV remains LOW during the conversion and is still LOW at the
start of the 13th clock cycle. (2) The low power mode is exited when CONV goes HIGH. (3) When in power-down, the transition from
hold mode to sample mode is initiated by CONV going HIGH.
(1) (2)
(3)
FIGURE 4. Power-Down Timing.
D11
(MSB)
DATA
CONVERSION IN PROGRESSIDLE
LOW...
IDLE
CLK
CONV
POWER MODE FULL POWER LOW POWER
D10 D1
D0
(LSB)
1 2 3 121314 2324
D1 D10
D11
(MSB)
INTERNAL
CONVERSION
STAT E
t
CVDD
t
CKCS
t
CKCH
t
CVPD
t
CVH
HOLDSAMPLE
SAMPLE/HOLD
MODE
NOTES: (1) The serial data can be transmitted LSB-first by pulling CONV LOW during the 13th clock cycle. (2) After the MSB has been
transmitted, the DATA output pin will remain LOW until CONV goes HIGH. (3) When CONV is taken LOW to initiate the LSB first transfer,
the converter enters the power-down mode.
(1) (2)
(3)
FIGURE 5. Serial Data “LSB-First” Timing.
typical performance curve “Supply Current vs Sample Rate.”
In contrast, the second method (clocking at a fixed rate)
means that each conversion takes X clock cycles. As the
time between conversions get longer, the converter remains
in power-down an increasing percentage of time. This re-
duces total power consumption by a considerable amount.
For example, a 50kHz conversion rate results in roughly
1/10 of the power (minus the reference) that is used at a