Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal VSSOP 8

1 ADS7835

ADS7835

DESCRIPTION

The ADS7835 is a 12-bit, sampling analog-to-digi-

tal converter (A/D) complete with sample-and-hold

(S/H), internal 2.5V reference, and synchronous

serial interface. Typical power dissipation is 17.5mW

at a 500kHz throughput rate. The device can be

placed into a power-down mode which reduces dis-

sipation to just 2.5mW. The input range is –V

REF

, and the internal reference can be overdriven

by an external voltage.

Low power, small size, and high speed make the

ADS7835 ideal for battery-operated systems such

as wireless communication devices, portable multi-

channel data loggers, and spectrum analyzers. The

serial interface also provides low cost isolation for

remote data acquisition. The ADS7835 is avail-

able in an MSOP-8 package and is guaranteed over

the –40°C to +85°C temperature range.

12-Bit, High-Speed, Low Power Sampling

ANALOG-TO-DIGITAL CONVERTER

FEATURES

● 500kHz THROUGHPUT RATE

● 2.5V INTERNAL REFERENCE

● LOW POWER: 17.5mW

● SINGLE SUPPLY +5V OPERATION

● SERIAL INTERFACE

● GUARANTEED NO MISSING CODES

● MSOP-8

● ±V

REF

INPUT RANGE

APPLICATIONS

● BATTERY-OPERATED SYSTEMS

● DIGITAL SIGNAL PROCESSING

● HIGH-SPEED DATA ACQUISITION

● WIRELESS COMMUNICATION SYSTEMS

1998 Burr-Brown Corporation PDS-1478B Printed in U.S.A.May, 2000

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111

Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

SAR

CLK

Serial

Interface

Comparator

S/H Amp

DATA

±2.5V

Input

CDAC

Internal

+2.5V Ref

Buffer

REF

CONV

10kΩ ±30%

2kΩ

For most current data sheet and other product

information, visit www.burr-brown.com

SBAS102

Summary of content (20 pages)

PAGE 1
ADS7835 ® For most current data sheet and other product information, visit www.burr-brown.com 12-Bit, High-Speed, Low Power Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● 500kHz THROUGHPUT RATE The ADS7835 is a 12-bit, sampling analog-to-digital converter (A/D) complete with sample-and-hold (S/H), internal 2.5V reference, and synchronous serial interface. Typical power dissipation is 17.5mW at a 500kHz throughput rate.
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SPECIFICATIONS At TA = –40°C to +85°C, +VCC = +5V, fSAMPLE = 500kHz, fCLK = 16 • fSAMPLE, and internal +2.5V reference, unless otherwise specified. ADS7835E PARAMETER CONDITIONS MIN RESOLUTION TYP ADS7835EB MAX MIN Input Capacitance Input Resistance ±2.5V with the 2.
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ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC DISCHARGE SENSITIVITY +VCC to GND ............................................................................ –0.3V to 6V Analog Inputs to GND ............................................................. –5.3 to +5.3 Digital Inputs to GND ............................................... –0.3V to (VCC + 0.3V) Power Dissipation .......................................................................... 325mW Maximum Junction Temperature .............................
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TYPICAL PERFORMANCE CURVES At TA = +25°C, +VCC = +5V, fSAMPLE = 500kHz, fCLK = 16 • fSAMPLE, and internal +2.5V reference, unless otherwise specified. CHANGE IN BIPOLAR OFFSET ERROR vs TEMPERATURE CHANGE IN FULL-SCALE ERRORS vs TEMPERATURE 0.6 1.0 Negative Full-Scale Error 0.4 Delta from +25°C (LSB) Delta from +25°C (LSB) 0.0 –1.0 –2.0 Positive Full-Scale Error –3.0 –4.0 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –5.0 –40 –1.
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TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, +VCC = +5V, fSAMPLE = 500kHz, fCLK = 16 • fSAMPLE, and internal +2.5V reference, unless otherwise specified. PEAK-TO-PEAK NOISE vs EXTERNAL REFERENCE VOLTAGE CHANGE END-POINT ERRORS vs EXTERNAL REFERENCE VOLTAGE 0.90 3.0 0.85 Peak-to-Peak Noise (LSB) Delta from VREF = 2.5V (LSB) 4.0 Negative Full-Scale Error 2.0 1.0 0.0 –1.0 –2.0 Positive Full-Scale Error and Bipolar Offset Error –3.0 0.80 0.75 0/70 0.65 0.60 0.55 –4.0 0.50 –5.0 2.2 2.4 2.
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TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, +VCC = +5V, fSAMPLE = 500kHz, fCLK = 16 • fSAMPLE, and internal +2.5V reference, unless otherwise specified.
PAGE 7
THEORY OF OPERATION the device is in the sample or hold mode. When sampling, the input has a 4kΩ input impedance to the reference. The source of the analog input voltage must be able to charge the input impedance (typically 25pF || 1kΩ) to a 12-bit settling level within the same period. This can be as little as 350ns in some operating modes. When the converter is in the hold mode, the input impedance switches to approximately 2kΩ to ground.
PAGE 8
the CLK may be kept LOW or HIGH. EXTERNAL REFERENCE The asynchronous nature of CONV to CLK raises some interesting possibilities, but also some design considerations. Figure 3 shows that CONV has timing restraints in relation to CLK (tCKCH and tCKCS). However, if these times are violated (which could happen if CONV is completely asynchronous to CLK), the converter will perform a conversion correctly, but the exact timing of the conversion is indeterminate.
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clock cycle is the first of the conversion.) tween conversions. In addition, if CONV is completely asynchronous to CLK and CLK is continuous, there is the possibility that CLK will transition just prior to CONV going LOW. If this occurs faster than the 10ns indicated by tCKCH, there is a chance that some digital feedthrough may be coupled onto the hold capacitor. This could cause a small offset error for that particular conversion.
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CONV 1 CLK 2 D11 (MSB) DATA 3 12 D10 D1 13 D0 (LSB) tCVSP SAMPLE/HOLD SAMPLE MODE tACQ HOLD SAMPLE HOLD (3) INTERNAL CONVERSION STATE IDLE CONVERSION IN PROGRESS IDLE tCKPD tCVPU POWER MODE FULL POWER LOW POWER (1) FULL POWER (2) NOTES: (1) The low power mode (“power-down”) is entered when CONV remains LOW during the conversion and is still LOW at the start of the 13th clock cycle. (2) The low power mode is exited when CONV goes HIGH.
PAGE 11
500kHz conversion rate. HIGH. SHORT-CYCLE TIMING fSAMPLE POWER WITH CLK = 16 • fSAMPLE POWER WITH CLK = 8MHz 500kHz 17.5mW 17.5mW 250kHz 16.5mW 13.5mW 100kHz 15.5mW 10.5mW The conversion currently in progress can be “short-cycled” with the technique shown in Figure 6. This term means that the conversion will terminate immediately, before all 12 bits have been decided. This can be a very useful feature when a resolution of 12 bits is not needed.
PAGE 12
logic. Figure 7 shows a timing diagram that might be used with a typical digital signal processor such as a TI DSP. For the Buffered Serial Port (BSP) on the TMS320C54X family, CONV would tied to BFSX, CLK would be tied to BCLKX, and DATA would be tied to BDR. DATA FORMAT The ADS7835 output data is in Binary Two’s Complement format as shown in Table III.
PAGE 13
(tCKP). larger capacitor and a 5Ω or 10Ω series resistor may be used to lowpass filter a noisy supply. LAYOUT The ADS7835 draws very little current from an external reference on average as the reference voltage is internally buffered. However, glitches from the conversion process appear at the VREF input and the reference source must be able to handle this. Whether the reference is internal or external, the VREF pin should be bypassed with a 0.1µF capacitor.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PAGE 16
PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS7835E/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS7835EB/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.
PAGE 17
PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7835E/250 VSSOP DGK 8 250 210.0 185.0 35.0 ADS7835EB/250 VSSOP DGK 8 250 210.0 185.0 35.
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