Datasheet

ADS7834
12
SBAS098A
www.ti.com
D11
(MSB)
DATA
CLK
CONV
D10 D1
D0
(LSB)
231 4 13 14 15 16 1 2 3
D11
(MSB)
t
ACQ
t
DRP
FIGURE 7. Ideal Input Voltages and Output Codes.
DSP INTERFACING
Figure 8 shows a timing diagram that might be used with a
typical digital signal processor such as a TI DSP. For the
buffered serial port (BSP) on the TMS320C54X family,
CONV would tied to BFSX, CLK would be tied to BCLKX,
and DATA would be tied to BDR.
SPI/QSPI INTERFACING
Figure 9 shows the timing diagram for a typical serial
peripheral interface (SPI) or queued serial peripheral inter-
face (QSPI). Such interfaces are found on a number of
microcontrollers form various manufacturers. CONV would
be tied to a general purpose I/O pin (SPI) or to a PCX pin
(QSPI), CLK would be tied to the serial clock, and DATA
would be tied to the serial input data pin such as MISO
(master in slave out).
Note the time t
DRP
shown in Figure 9. This represents the
maximum amount of time between CONV going LOW and
the start of the conversion clock. Since CONV going LOW
places the sample and hold in the hold mode and because the
hold capacitor loses charge over time, there is a requirement
that time t
DRP
be met as well as the maximum clock period
(t
CKP
).
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS7834 circuitry. This is particu-
larly true if the CLK input is approaching the maximum
input rate.
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connec-
tions, and digital inputs that occur just prior to latching the
output of the analog comparator. Thus, during any single
conversion for an n-bit SAR converter, there are n “win-
dows” in which large external transient voltages can easily
affect the conversion result. Such glitches might originate
from switching power supplies, nearby digital logic, and
high power devices. The degree of error in the digital output
depends on the reference voltage, layout, and the exact
timing of the external event. The error can change if the
external event changes in time with respect to the CLK
input.
FIGURE 8. Typical DSP Interface Timing.
D11
(MSB)
DATA
CLK
CONV
D10 D1
D0
(LSB)
1215 16 3 12 13 14 15 16 1 2 3 4
D11
(MSB)
D10 D9
FIGURE 9. Typical SPI/QSPI Interface Timing.
Input Voltage
(2)
(V)
Output Code
0V
FS = Full-Scale Voltage = V
REF
1 LSB = FS/4096
2.499V
(1)
00...010
00...001
00...000
11...101
11...110
11...111
1 LSB
NOTES: (1) For external reference, value is V
REF
– 1 LSB. (2) Voltage
at converter input: +IN – (–IN).