Datasheet

ADS7830
SBAS302C –DECEMBER 2003–REVISED OCTOBER 2012 www.ti.com
TIMING CHARACTERISTICS
(1)
(continued)
At T
A
= –40°C to +125°C and +V
DD
= +2.7V, unless otherwise noted.
PARAMETER SYMBOL CONDITIONS MIN MAX UNIT
Standard Mode 0 3.45 µs
Fast Mode 0 0.9 µs
Data Hold Time t
HD; DAT
High-Speed Mode, C
B
= 100pF max
(3)
0
(4)
70 ns
High-Speed Mode, C
B
= 400pF max
(3)
0
(4)
150 ns
Standard Mode 1000 ns
Fast Mode 20 + 0.1C
B
300 ns
Rise Time of SCL Signal t
RCL
High-Speed Mode, C
B
= 100pF max
(3)
10 40 ns
High-Speed Mode, C
B
= 400pF max
(3)
20 80 ns
Standard Mode 1000 ns
Rise Time of SCL Signal After a
Fast Mode 20 + 0.1C
B
300 ns
Repeated START Condition and t
RCL1
High-Speed Mode, C
B
= 100pF max
(3)
10 80 ns
After an Acknowledge Bit
High-Speed Mode, C
B
= 400pF max
(3)
20 160 ns
Standard Mode 300 ns
Fast Mode 20 + 0.1C
B
300 ns
Fall Time of SCL Signal t
FCL
High-Speed Mode, C
B
= 100pF max
(3)
10 40 ns
High-Speed Mode, C
B
= 400pF max
(3)
20 80 ns
Standard Mode 1000 ns
Fast Mode 20 + 0.1C
B
300 ns
Rise Time of SDA Signal t
RDA
High-Speed Mode, C
B
= 100pF max
(3)
10 80 ns
High-Speed Mode, C
B
= 400pF max
(3)
20 160 ns
Standard Mode 300 ns
Fast Mode 20 + 0.1C
B
300 ns
Fall Time of SDA Signal t
FDA
High-Speed Mode, C
B
= 100pF max
(3)
10 80 ns
High-Speed Mode, C
B
= 400pF max
(3)
20 160 ns
Standard Mode 4.0 µs
Setup Time for STOP Condition t
SU; STO
Fast Mode 600 ns
High-Speed Mode 160 ns
Capacitive Load for SDA and
C
B
400 pF
SCL Line
Fast Mode 50 ns
Pulse Width of Spike Suppressed t
SP
High-Speed Mode 10 ns
Standard Mode 0.2V
DD
V
Noise Margin at the HIGH Level
for Each Connected Device V
NH
Fast Mode 0.2V
DD
V
(Including Hysteresis)
High-Speed Mode 0.2V
DD
V
Standard Mode 0.1V
DD
V
Noise Margin at the LOW Level
for Each Connected Device V
NL
Fast Mode 0.1V
DD
V
(Including Hysteresis)
High-Speed Mode 0.1V
DD
V
(3) For bus line loads C
B
between 100pF and 400pF the timing parameters must be linearly interpolated.
(4) A device must internally provide a data hold time to bridge the undefined part between V
IH
and V
IL
of the falling edge of the SCLH
signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.
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