Datasheet

Sr A
1
1 0 0 1 0 A
0
R A D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
N P
S A
1
1 0 0 1 10 A
0
W A SD C
2
C
1
C
0
PD
0
X X A
S A
1
1 0 0 1 10 A
0
W A XXXXXX X A P
Wait until the required
settling time is reached
Settled Internal Reference
Settled Internal Reference
Typical Read
Sequence
in F/S Mode
(1)
From Master to Slave
A = acknowledge (SDA LOW)
N = not acknowledge (SDA HIGH)
S = START Condition
P = STOP Condition
Sr = repeated START condition
W = '0' (WRITE)
R = '1' (READ)
From Slave to Master
Command ByteWrite-Addressing Byte
Command ByteWrite-Addressing Byte
ADC Power-Down Mode ADC Sampling Mode
ADC Converting Mode
ADC Power-Down Mode
(depending on power-down selection bits)
Read-Addressing Byte 1 x (8 Bits + not-ack)
See Note (2)
Internal Reference Turn-On Sequence
Internal Reference
Turn-On
Settling Time
ADS7830
SBAS302C –DECEMBER 2003–REVISED OCTOBER 2012 www.ti.com
(1) Typical read sequences can be reused after the internal reference is settled.
(2) To secure bus operation and loop back to the stage of write-addressing for next conversion, use repeated START.
Figure 17. Internal Reference Turn-On Sequence and Typical Read Sequence (F/S mode shown)
The ADS7830 architecture offers no inherent
LAYOUT
rejection of noise or voltage variation in regards to
using an external reference input. This is of particular
For optimum performance, care should be taken with
concern when the reference input is tied to the power
the physical layout of the ADS7830 circuitry. The
supply. Any noise and ripple from the supply will
basic SAR architecture is sensitive to glitches or
appear directly in the digital results. While high-
sudden changes on the power supply, reference,
frequency noise can be filtered out, voltage variation
ground connections, and digital inputs that occur just
due to line frequency (50Hz or 60Hz) can be difficult
prior to latching the output of the analog comparator.
to remove.
Therefore, during any single conversion for an “n-bit”
SAR converter, there are n “windows” in which large
The GND pin should be connected to a clean ground
external transient voltages can easily affect the
point. In many cases, this will be the “analog” ground.
conversion result. Such glitches might originate from
Avoid connections that are too near the grounding
switching power supplies, nearby digital logic, and
point of a microcontroller or digital signal processor.
high-power devices.
The ideal layout will include an analog ground plane
dedicated to the converter and associated analog
With this in mind, power to the ADS7830 should be
circuitry.
clean and well-bypassed. A 0.1μF ceramic bypass
capacitor should be placed as close to the device as
possible. A 1μF to 10μF capacitor may also be
needed if the impedance of the connection between
+V
DD
and the power supply is high.
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