Datasheet
ADS7828
2
SBAS181C
www.ti.com
MAXIMUM
INTEGRAL SPECIFIED
LINEARITY PACKAGE TEMPERATURE ORDERING TRANSPORT
PRODUCT ERROR (LSB) PACKAGE-LEAD DESIGNATOR RANGE NUMBER MEDIA, QUANTITY
ADS7828E ±2 TSSOP-16 PW –40°C to +85°C ADS7828E/250 Tape and Reel, 250
"""""ADS7828E/2K5 Tape and Reel, 2500
ADS7828EB ±1 TSSOP-16 PW –40°C to +85°C ADS7828EB/250 Tape and Reel, 250
"""""ADS7828EB/2K5 Tape and Reel, 2500
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI web site at www.ti.com.
PACKAGE/ORDERING INFORMATION
(1)
ABSOLUTE MAXIMUM RATINGS
(1)
+V
DD
to GND ........................................................................ –0.3V to +6V
Digital Input Voltage to GND ................................. –0.3V to +V
DD
+ 0.3V
Operating Temperature Range ...................................... –40°C to +105°C
Storage Temperature Range ......................................... –65°C to +150°C
Junction Temperature (T
J
max) .................................................... +150°C
TSSOP Package
Power Dissipation .................................................... (T
J
max – T
A
)/
θ
JA
θ
JA
Thermal Impedance ........................................................ 240°C/W
Lead Temperature, Soldering
Vapor Phase (60s) ............................................................ +215°C
Infrared (15s) ..................................................................... +220°C
NOTE: (1) Stresses above those listed under
Absolute Maximum Ratings
may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper han-
dling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PIN CONFIGURATION
Top View TSSOP
PIN DESCRIPTIONS
PIN NAME DESCRIPTION
1 CH0 Analog Input Channel 0
2 CH1 Analog Input Channel 1
3 CH2 Analog Input Channel 2
4 CH3 Analog Input Channel 3
5 CH4 Analog Input Channel 4
6 CH5 Analog Input Channel 5
7 CH6 Analog Input Channel 6
8 CH7 Analog Input Channel 7
9 GND Analog Ground
10 REF
IN
/ REF
OUT
Internal +2.5V Reference, External Reference Input
11 COM Common to Analog Input Channel
12 A0 Slave Address Bit 0
13 A1 Slave Address Bit 1
14 SCL Serial Clock
15 SDA Serial Data
16 +V
DD
Power Supply, 3.3V Nominal
1
2
3
4
5
6
7
8
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
+V
DD
SDA
SCL
A1
A0
COM
REF
IN
/ REF
OUT
GND
16
15
14
13
12
11
10
9
ADS7828