Datasheet

9
®
ADS7825
Hi-Z State
BUSY
R/C
DATA
BUS
High Byte
t
3
t
4
t
21
t
21
t
1
t
21
t
21
BYTE
t
21
t
21
t
21
t
21
t
21
t
21
Hi-Z State Low Byte Hi-Z State
t
9
t
12
t
9
t
12
CS
FIGURE 2. Conversion Timing with Parallel Output (CS LOW).
t
10
BUSY
R/C
MODE
Acquire
Convert
t
11
t
7
t
6
t
3
t
4
t
1
Acquire Convert
t
8
t
6
t
3
Parallel
Data Bus
Previous
High Byte Valid
t
12
Hi-Z Not Valid
t
2
t
9
High Byte
Valid
t
12
t
9
t
12
BYTE
t
1
Previous Low
Byte Valid
Previous High
Byte Valid
Low Byte
Valid
High Byte
Valid
t
12
Hi-Z
t
12
t
12
t
5
FIGURE 3. Using CS to Control Conversion and Read Timing with Parallel Outputs.
FIGURE 4. Serial Data Timing Using Internal Data Clock (TAG LOW).
1
MSB Valid
Hi-Z
CS or R/C
(1)
DATACLK
SDATA
BUSY
t
7
+ t
8
t
16
t
15
t
14
t
26
t
13
t
25
2 3 15 16
Bit 14 Valid Bit 1 ValidBit 13 Valid LSB Valid
Hi-Z
NOTE: (1) If controlling with CS, tie R/C LOW. If controlling with R/C, tie CS LOW.
1
MSB Valid
2
Bit 14 Valid
(Results from previous conversion.)