Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal SOIC 28

ADS7824

into the A0 and A1 registers (pins 19 and 18, respectively)

prior to CONTC being raised HIGH, becomes the first

address in the sequential continuous conversion mode (e.g.,

if Channel 1 was the last address selected then Channel 2 will

follow, then Channel 3, and so on). The A0 and A1 address

inputs become outputs when the device is in this mode.

When BUSY rises at the end of a conversion, A0 and A1 will

output the address of the channel that will be converted when

BUSY goes LOW at the beginning of the next conversion.

Data will be valid for the previous channel after BUSY rises.

The address lines are updated when BUSY rises. See Table

IVa and Figure 7 for channel selection timing in continuous

conversion mode.

PWRD (pin 26) can be used to reset the multiplexer address

to zero. With the ADS7824 configured for no conversion,

PWRD can be taken HIGH for a minimum of 200ns. When

PWRD returns LOW, the multiplexer address will be reset to

zero. When the continuous conversion mode is enabled, the

first conversion will be done on Channel 0. Subsequent

conversions will proceed through each higher channel,

cycling back to zero after Channel 3.

If PWRD is held HIGH for a significant period of time, the

REF (pin 7) bypass capacitor may discharge (if the internal

reference is being utilized) and the CAP (pin 6) bypass

capacitor will discharge (for both internal and external

references). The continuous conversion mode should not be

enabled until the bypass capacitor(s) have recharged and

stabilized (1ms for 2.2µF capacitors recommended). In

addition, the continuous conversion mode should not be

enabled even with a short pulse on PWRD until the mini-

mum acquisition time has been met.

MANUAL CHANNEL SELECTION (CONTC= 0V)

The channels of the ADS7824 can be selected manually by

using the A0 and A1 address pins (pins 19 and 18, respec-

tively). See Table IVb for the multiplexer truth table and

Figure 8 for channel selection timing.

FIGURE 8. Channel Addressing in Normal Conversion Mode (CONTC and CS LOW).

CHANNEL SELECTED

A1 A0 WHEN BUSY GOES HIGH DESCRIPTION OF OPERATION

0 0 AIN

0 1 AIN

1 0 AIN

1 1 AIN

Channel to be converted during conversion 'n + 1' is latched

when conversion 'n' is initiated (BUSY goes LOW). The selected

input starts being acquired as soon as conversion 'n' is done

(BUSY goes HIGH).

TABLE IVb. A0 and A1 Inputs (CONTC LOW).

ADS7824 TIMING AND CONTROL

0 0 AIN

AIN

0 1 AIN

AIN

1 0 AIN

AIN

1 1 AIN

AIN

DATA AVAILABLE CHANNEL TO BE

A1 A0 FROM CHANNEL OR BEING CONVERTED DESCRIPTION OF OPERATION

Channel being acquired or converted is output on these

address lines. Data is valid for the previous channel. These

lines are updated when BUSY rises.

TABLE IVa. A0 and A1 Outputs (CONTC HIGH).

FIGURE 7. Channel Addressing in Continuous Conversion Mode (CONTC HIGH, CS and R/C LOW).

R/C

BUSY

A0, A1

(Input)

D7-D0 n – 3 n – 2 n – 1 n n + 1 n + 2 n + 3

n – 1 n n + 1 n + 2 n + 3 n + 4 n + 5

n + 4n + 3n + 2n + 1nn – 1n – 2

n + 4

Conversion Currently in Progress:

Channel Address for Conversion:

Results from Conversion: