Datasheet
12
®
ADS7824
READING DATA
PARALLEL OUTPUT
To use the parallel output, tie PAR/SER (pin 20) HIGH. The
parallel output will be active when R/C (pin 22) is HIGH and
CS (pin 23) is LOW. Any other combination of CS and R/C
will tri-state the parallel output. Valid conversion data can be
read in two 8-bit bytes on D7-D0 (pins 9-13 and 15-17). When
BYTE (pin 21) is LOW, the 8 most significant bits will be
valid with the MSB on D7. When BYTE is HIGH, the 4 least
significant bits will be valid with the LSB on D4. BYTE can
be toggled to read both bytes within one conversion cycle.
Upon initial power up, the parallel output will contain
indeterminate data.
PARALLEL OUTPUT (After a Conversion)
After conversion ‘n’ is completed and the output registers
have been updated, BUSY (pin 24) will go HIGH. Valid data
from conversion ‘n’ will be available on D7-D0 (pins 9-13
and 15-17). BUSY going HIGH can be used to latch the
data. Refer to Table II and Figures 2 and 3 for timing
constraints.
PARALLEL OUTPUT (During a Conversion)
After conversion ‘n’ has been initiated, valid data from
conversion ‘n – 1’ can be read and will be valid up to 12µs
TABLE II. Conversion, Data, and Address Timing. T
A
= –40°C to +85°C.
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
1
Convert Pulse Width 0.04 12 µs
t
2
Start of Conversion to New Data Valid 15 21 µs
t
3
Start of Conversion to BUSY LOW 85 ns
t
4
BUSY LOW 15 21 µs
t
5
End of Conversion to BUSY HIGH 90 ns
t
6
Aperture Delay 40 ns
t
7
Conversion Time 15 21 µs
t
8
Acquisition Time 35µs
t
7
+ t
8
Throughput Time 25 µs
t
9
Bus Relinquish Time 10 83 ns
t
10
Data Valid to BUSY HIGH 20 60 ns
t
11
Start of Conversion to Previous Data Not Valid 12 15 µs
t
12
Bus Access Time and BYTE Delay 83 ns
t
13
Start of Conversion to DATACLK Delay 1.4 µs
t
14
DATACLK Period 1.1 µs
t
15
Data Valid to DATACLK HIGH 20 75 ns
t
16
DATACLK LOW to Data Not Valid 400 600 ns
t
17
External DATACLK Period 100 ns
t
18
External DATACLK HIGH 50 ns
t
19
External DATACLK LOW 40 ns
t
20
CS LOW and R/C HIGH to External DATACLK HIGH (Enable Clock) 25 ns
t
21
R/C to CS Setup Time 10 ns
t
22
CS HIGH or R/C LOW to External DATACLK HIGH (Disable Clock) 25 ns
t
23
DATACLK HIGH to SYNC HIGH 15 35 ns
t
24
DATACLK HIGH to Valid Data 25 55 ns
t
25
Start of Conversion to SDATA Active 83 ns
t
26
End of Conversion to SDATA Tri-State 83 ns
t
27
CS LOW and R/C HIGH to SDATA Active 83 ns
t
28
CS HIGH or R/C LOW to SDATA Tri-State 83 ns
t
29
BUSY HIGH to Address Valid 20 ns
t
30
Address Valid to BUSY LOW 500 ns
after the start of conversion ‘n’. Do not attempt to read data
beyond 12µs after the start of conversion ‘n’ until BUSY
(pin 24) goes HIGH; this may result in reading invalid data.
Refer to Table II and Figures 2 and 3 for timing constraints.
SERIAL OUTPUT
When PAR/SER (pin 20) is LOW, data can be clocked out
serially with the internal data clock or an external data clock.
When EXT/INT (pin 12) is LOW, DATACLK (pin 15) is an
output and is always active regardless of the state of CS (pin
23) and R/C (pin 22). The SDATA output is active when
BUSY (pin 24) is LOW. Otherwise, it is in a tri-state
condition. When EXT/INT is HIGH, DATACLK is an input.
The SDATA output is active when CS is LOW and R/C is
HIGH. Otherwise, it is in a tri-state condition. Regardless of
the state of EXT/INT, SYNC (pin 13) is an output and always
active, while TAG (pin 17) is always an input.
INTERNAL DATA CLOCK (During A Conversion)
To use the internal data clock, tie EXT/INT (pin 12) LOW.
The combination of R/C (pin 22) and CS (pin 23) LOW will
initiate conversion ‘n’ and activate the internal data clock
(typically 900kHz clock rate). The ADS7824 will output 12
bits of valid data, MSB first, from conversion ‘n – 1’ on
SDATA (pin 16), synchronized to 12 clock pulses output on
DATACLK (pin 15). The data will be valid on both the