Datasheet

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Short Cycling
10.0
8.0
6.0
4.0
2.0
0.0
0.00
SupplyCurrent( A)m
0.1 1 10 100
SampleRate(kHz)
0.050
T =25 C°
A
V =2.7V
CC
V =2.5V
REF
f =16 f·
CLK SAMPLE
CS LOW(GND)
CS HIGH(V )CC
ADS7822
SBAS062C – JANUARY 1996 – REVISED AUGUST 2007
There is an important distinction between the
power-down mode that is entered after a conversion
Power dissipation can also be reduced by lowering
is complete and the full power-down mode that is
the power-supply voltage and the reference voltage.
enabled when CS is high. While both shutdown the
The ADS7822 operates over a V
CC
range of 2.0V to
analog section, the digital section is completely
5.25V. It will run up to a 200kHz throughput rate over
shutdown only when CS is high. Thus, if CS is left
a supply range of 4.75V to 5.25V; therefore, it can be
low at the end of a conversion and the converter is
clocked at up to 3.2MHz. However, at voltages below
continually clocked, the power consumption will not
2.7V, the converter does not run at a 75kHz sample
be as low as when CS is high; see Figure 26 for more
rate. See the Typical Characteristic curves for more
information.
information regarding power-supply voltage and
maximum sample rate.
Another way of saving power is to use the CS signal
to short-cycle the conversion. Because the ADS7822
places the latest data bit on the D
OUT
line as it is
generated, the converter can easily be short-cycled.
This term means that the conversion can be
terminated at any time. For example, if only eight bits
of the conversion result are needed, then the
conversion can be terminated (by pulling CS high)
after the eighth bit has been clocked out.
This technique can be used to lower the power
dissipation (or to increase the conversion rate) in
those applications where an analog signal is being
monitored until some condition becomes true. For
Figure 26. Shutdown Current with CS High is
Typically 50nA, Regardless of the Clock. example, if the signal is outside a predetermined
Shutdown Current with CS Low varies with
range, the full 12-bit conversion result may not be
Sample Rate.
needed. If so, the conversion can be terminated after
the first n-bits, where n might be as low as 3 or 4.
This results in lower power dissipation in both the
converter and the rest of the system, because they
spend more time in the power-down mode.
14 Submit Documentation Feedback Copyright © 1996 – 2007, Texas Instruments Incorporated
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