Datasheet

www.ti.com
Data Format
1000
100
10
1
SupplyCurrent( A)m
0.1 1 10 100
SampleRate(kHz)
V =5.0V
CC
V =5.0V
REF
V =2.7V
CC
V =2.5V
REF
T =25 C°
A
f =1.2MHz
CLK
POWER DISSIPATION
1000
100
10
1
SupplyCurrent( A)m
0.1 1 10 100
SampleRate(kHz)
T =25 C°
A
V =2.7V
CC
V =2.5V
REF
f =16 f·
CLK SAMPLE
ADS7822
SBAS062C – JANUARY 1996 – REVISED AUGUST 2007
A falling CS signal initiates the conversion and data transition (as is typical for digital CMOS components),
transfer. The first 1.5 to 2.0 clock periods of the but also uses some current for the analog circuitry,
conversion cycle are used to sample the input signal. such as the comparator. The analog section
After the second falling DCLOCK edge, D
OUT
is dissipates power continuously, until the power-down
enabled and outputs a low value for one clock period. mode is entered.
For the next 12 DCLOCK periods, D
OUT
outputs the
Figure 24 shows the current consumption of the
conversion result, most significant bit first.
ADS7822 versus sample rate. For this graph, the
After the least significant bit (B0) has been output, converter is clocked at 1.2MHz regardless of the
subsequent clocks repeat the output data, but in a sample rate — CS is high for the remaining sample
least significant bit first format. After the most period. Figure 25 also shows current consumption
significant bit (B11) has been repeated, DOUT will versus sample rate. However, in this case, the
tri-state. Subsequent clocks have no effect on the DCLOCK period is 1/16th of the sample period — CS
converter. A new conversion is initiated only when CS is high for one DCLOCK cycle out of every 16.
is taken high and returned low.
The output data from the ADS7822 is in straight
binary format, as shown in Table 2 . This table
represents the ideal output code for the given input
voltage and does not include the effects of offset,
gain error, or noise.
Table 2. Ideal Input Voltages and Output Codes
DIGITAL OUTPUT
DESCRIPTION ANALOG VALUE
STRAIGHT BINARY
Full-Scale range V
REF
Least significant
V
REF
/4096
bit (LSB) BINARY CODE HEX CODE
Full-Scale V
REF
– 1 LSB 1111 1111 1111 FFF
Figure 24. Maintaining f
CLK
at the Highest
Midscale V
REF
/2 1000 0000 0000 800
Possible Rate Allows the Supply Current to Drop
Midscale – 1 LSB V
REF
/2 – 1 LSB 0111 1111 1111 7FF
Linearly with the Sample Rate
Zero 0V 0000 0000 0000 000
The architecture of the converter, the semiconductor
fabrication process, and a careful design allow the
ADS7822 to convert at up to a 75kHz rate while
requiring very little power. Still, for the absolute
lowest power dissipation, there are several things to
keep in mind.
The power dissipation of the ADS7822 scales directly
with conversion rate. So, the first step to achieving
the lowest power dissipation is to find the lowest
conversion rate that will satisfy the requirements of
the system.
In addition, the ADS7822 goes into power-down
mode under two conditions: when the conversion is
complete and whenever CS is high (see Figure 22 ).
Figure 25. Scaling f
CLK
Reduces the Supply
Current Only Slightly with the Sample Rate
Ideally, each conversion should occur as quickly as
possible; preferably, at a 1.2MHz clock rate. This
way, the converter spends the longest possible time
in the power-down mode. This is very important since
the converter not only uses power on each DCLOCK
Copyright © 1996 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): ADS7822