Datasheet

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D
OUT
1.4V
TestPoint
3kW
100pF
C
LOAD
LoadCircuitfort ,t ,andt
dDO r f
VoltageWaveformsforD RiseandFallTimes,t ,t
OUT r f
VoltageWaveformsforD DelayTimes,t
OUT dDO
VoltageWaveformsfort
dis
VoltageWaveformsfort
en
LoadCircuitfort andt
dis en
t
r
D
OUT
V
OH
V
OL
t
f
D
OUT
TestPoint
t Waveform2,t
dis en
V
CC
t Waveform1
dis
100pF
C
LOAD
3kW
t
dis
CS/SHDN
D
OUT
Waveform1
(1)
D
OUT
Waveform2
(2)
90%
10%
V
IH
1
B11
2
t
en
CS/SHDN
DCLOCK
V
OL
D
OUT
t
dDO
D
OUT
DCLOCK
V
OH
V
OL
V
IL
t
hDO
NOTES:(1)Waveform1isforanoutputwithinternalconditionssuchthattheoutput
isHIGHunlessdisabledbytheoutputcontrol.
(2)Waveform2isforanoutputwithinternalconditionssuchthattheoutput
isLOWunlessdisabledbytheoutputcontrol.
ADS7822
SBAS062C – JANUARY 1996 – REVISED AUGUST 2007
Table 1. Timing Specifications ( – 40 ° C to +85 ° C)
V
CC
= 2.7V V
CC
= 5V
SYMBOL DESCRIPTION UNITS
MIN TYP MAX MIN TYP MAX
t
SMPL
Analog input sample time 1.5 2.0 1.5 2.0 Clk Cycles
t
CONV
Conversion time 12 12 Clk Cycles
t
CYC
Cycle time 16 16 Clk Cycles
t
CSD
CS falling to DCLOCK low 0 0 ns
t
SUCS
CS falling to DCLOCK rising 0.03 1000 0.03 1000 μ s
t
hDO
DCLOCK falling to current D
OUT
not valid 15 15 ns
t
dDO
DCLOCK falling to next D
OUT
valid 130 200 85 150 ns
t
dis
CS rising to D
OUT
tri-state 40 80 25 50 ns
t
en
DCLOCK falling to D
OUT
enabled 75 175 50 100 ns
t
f
D
OUT
fall time 90 200 70 100 ns
t
r
D
OUT
rise time 110 200 60 100 ns
Figure 23. Timing Diagrams and Test Circuits for the Parameters in Table 1
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