Datasheet

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THEORY OF OPERATION
REFERENCE INPUT
ANALOG INPUT
ADS7822
SBAS062C – JANUARY 1996 – REVISED AUGUST 2007
The ADS7822 is a classic successive approximation The range of the – In input is limited to – 0.2V to +1V.
register (SAR) A/D converter. The architecture is Because of this, the differential input can be used to
based on capacitive redistribution that inherently reject only small signals that are common to both
includes a sample/hold function. The converter is inputs. Thus, the – In input is best used to sense a
fabricated on a 0.6 μ CMOS process. The architecture remote signal ground that may move slightly with
and process allow the ADS7822 to acquire and respect to the local ground potential.
convert an analog signal at up to 200,000
The input current on the analog inputs depends on a
conversions per second while consuming very little
number of factors: sample rate, input voltage, source
power.
impedance, and power-down mode. Essentially, the
The ADS7822 requires an external reference, an current into the ADS7822 charges the internal
external clock, and a single power source (V
CC
). The capacitor array during the sample period. After this
external reference can be any voltage between 50mV capacitance has been fully charged, there is no
and V
CC
. The value of the reference voltage directly further input current. The source of the analog input
sets the range of the analog input. The reference voltage must be able to charge the input capacitance
input current depends on the conversion rate of the (25pF) to a 12-bit settling level within 1.5 clock
ADS7822. cycles. When the converter goes into the hold mode
or while it is in the power-down mode, the input
The external clock can vary between 10kHz (625Hz
impedance is greater than 1G Ω .
throughput) and 3.2MHz (200kHz throughput). The
duty cycle of the clock is essentially unimportant as Care must be taken regarding the absolute analog
long as the minimum high and low times are at least input voltage. To maintain the linearity of the
400ns for a supply range between 2.7V to 3.6V, or converter, the – In input should not drop below GND –
125ns for a supply range between 4.75V to 5.25V. 200mV or exceed GND + 1V. The +In input should
The minimum clock frequency is set by the leakage always remain within the range of GND – 200mV to
on the capacitors internal to the ADS7822. V
CC
+ 200mV. Outside of these ranges, the converter
linearity may not meet specifications.
The analog input is provided to two input pins: +In
and – In. When a conversion is initiated, the
differential input on these pins is sampled on the
internal capacitor array. While a conversion is in
The external reference sets the analog input range.
progress, both inputs are disconnected from any
The ADS7822 operates with a reference in the range
internal function.
of 50mV to V
CC
. There are several important
implications of this.
The digital result of the conversion is clocked out by
the DCLOCK input and is provided serially, most
As the reference voltage is reduced, the analog
significant bit first, on the D
OUT
pin. The digital data
voltage weight of each digital output code is reduced.
that is provided on the D
OUT
pin is for the conversion
This is often referred to as the LSB (least significant
currently in progress — there is no pipeline delay. It is
bit) size and is equal to the reference voltage divided
possible to continue to clock the ADS7822 after the
by 4096. This means that any offset or gain error
conversion is complete and to obtain the serial data
inherent in the A/D converter will appear to increase,
least significant bit first. See the Digital Interface
in terms of LSB size, as the reference voltage is
section for more information.
reduced.
The +In and – In input pins allow for a
pseudo-differential input signal. Unlike some
converters of this type, the – In input is not resampled
later in the conversion cycle. When the converter
goes into the hold mode, the voltage difference
between +In and – In is captured on the internal
capacitor array.
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