Datasheet

ADS7817
11
SBAS066A
D
OUT
1.4V
Test Point
3kΩ
100pF
C
LOAD
t
r
D
OUT
V
OH
V
OL
t
f
t
dDO
t
hDO
D
OUT
DCLOCK
V
OH
V
OL
V
IL
D
OUT
Test Point
t
dis
Waveform 2, t
en
t
dis
Waveform 1
100pF
C
LOAD
3kΩ
t
dis
CS/SHDN
D
OUT
Waveform 1
(1)
D
OUT
Waveform 2
(2)
90%
10%
V
IH
1
B11
2
t
en
CS/SHDN
DCLOCK
V
OL
D
OUT
V
CC
Load Circuit for t
dDO
, t
r
, and t
f
Voltage Waveforms for D
OUT
Rise and Fall Times t
r
, and t
f
Voltage Waveforms for D
OUT
Delay Times, t
dDO
Load Circuit for t
dis
and t
den
Voltage Waveforms for t
en
FIGURE 5. Timing Diagrams and Test Circuits for the Parameters in Table I.
Voltage Waveforms for t
dis
NOTES: (1) Waveform 1 is for an output with internal conditions such that
the output is HIGH unless disabled by the output control. (2) Waveform 2
is for an output with internal conditions such that the output is LOW unless
disabled by the output control.
1000
100
10
1
Supply Current (µA)
1 10 100 1000
Sample Rate (kHz)
T
A
= 25°C
V
CC
= +5V
V
REF
= +2.5V
f
CLK
= 3.2MHz
FIGURE 6. Maintaining f
CLK
at the Highest Possible Rate
Allows Supply Current to Drop Directly with
Sample Rate.
FIGURE 7. Scaling f
CLK
Reduces Supply Current Only
Slightly with Sample Rate.
1000
100
10
1
Supply Current (µA)
1 10 100 1000
Sample Rate (kHz)
T
A
= 25°C
V
CC
= +5V
V
REF
= +2.5V
f
CLK
= 16 • f
SAMPLE