Datasheet

ADS7812
9
SBAS042A
www.ti.com
BINARY TWO’S COMPLEMENT
DIGITAL OUTPUT
TABLE III. Ideal Input Voltage and Corresponding Digital Output for Two Common Input Ranges.
DESCRIPTION ANALOG INPUT
Full-Scale Range ±10V 0.5V to 4.5V
Least Significant Bit (LSB) 4.88mV 0.98mV BINARY CODE HEX CODE
+Full Scale –1LSB 9.99512V 4.49902V 0111 1111 1111 7FF
Midscale 0V 2.5V 0000 0000 0000 000
Midscale –1LSB –4.88mV 2.49902 V 1111 1111 1111 FFF
–Full Scale –10V 0.5V 1000 0000 0000 800
FIGURE 3. Block Diagram of the ADS7812’s Digital Inputs and Outputs.
READING DATA
The ADS7812’s digital output is in Binary Two’s Comple-
ment (BTC) format. Table III shows the relationship be-
tween the digital output word and the analog input voltage
under ideal conditions.
Figure 3 shows the relationship between the various digital
inputs, digital outputs, and internal logic of the ADS7812.
Figure 4 shows when the internal shift register of the
ADS7812 is updated and how this relates to a single conver-
sion cycle. Together, these two figures point out a very
important aspect of the ADS7812: the conversion result is
not available until after the conversion is complete. The
implications of this are discussed in the following sections.
FIGURE 4. Timing of the Shift Register Update.
QD
S0
Q
Update of the shift
register occurs just prior
to BUSY Rising
(1)
D
S1
QD
S2
QD
S10
QD
S11
Q
Shift Register
Working Register
Converter Core
D
SOUT
QD
W0
Q
Each flip-flop in the
working register is
latched as the
conversion proceeds
D
W1
QD
W2
QD
W10
QD
W11
•••
Delay
DATA
BUSY
DATACLK
CDAC
Control Logic
Clock
REF
EXT/INT
CONV
CS
NOTE: (1) If EXT/INT is HIGH (external clock), DATACLK is HIGH, and CS is LOW
during this time, the shift register will not be updated and the conversion result will be lost.
CONV
t
6
– t
25
t
25
BUSY
NOTE: Update of the internal shift register occurs in the
shaded region. If EXT/INT is HIGH, then DATACLK
must be LOW or CS must be HIGH during this time.