Datasheet

ADS7812
17
SBAS042A
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the DSP56002 must be programmed to enable the serial
interface when a LOW to HIGH transition on SCI occurs.
The DSP56002 can also provide the CONV signal, as shown
in Figure 17. The receive and transmit sections of the
interface are decoupled (asynchronous mode) and the trans-
mit section is set to generate a word length frame sync every
other transmit frame (frame rate divider set to 2). The
prescale modulus should be set to produce a transmit frame
at twice the desired conversion rate.
APPLICATIONS CIRCUIT
Figure 18 shows a multiplexed data acquisition circuit using
the ADS7812. The MPC508A provides the multiplexing
function while the OPA134 is configured as a Sallen-Key,
two-pole, unity gain lowpass filter.
CONV
BUSY
DATACLK
DATA
CS
EXT/INT
ADS7812
DSP56002
SC2
SC0
SRD
SYN = 0 (Asychronous)
GCK = 1 (Gated clock)
SCD2 = 1 (SC2 is an output)
SHFD = 0 (Shift MSB first)
WL1 = 0 WL0 = 1 (Word length = 12 bits)
FIGURE 17. DSP56002 Interface to the ADS7812. Processor Initiates Conversions.
In 1
In 2
In 3
In 4
In 5
In 6
In 7
In 8
A
0
A
1
A
2
MPC508A
R1
IN
R2
IN
R3
IN
BUF
BUSY
CONV
DATA
DATACLK
ADS7812
OPA134
C
2
330pF
C
1
2.2nF
R
1
1.4kΩ
R
2
15.4kΩ
+15V
±10V
Full Scale
–15V
µP
FIGURE 18. Multiplexed Data Acquisition Circuit.