Datasheet

ADS7812
12
SBAS042A
www.ti.com
External DATACLK Active After the Conversion
and During the Next Conversion
Figure 8 shows a method that is a hybrid of the two previous
approaches. This method works very well for microcontrollers
that do serial transfers 8 bits at a time and for slower
microcontrollers. For example, if the fastest serial clock that
the microcontroller can produce is 1µs, and two 8-bit trans-
fers must be used to obtain the serial data, the approach
shown in Figure 6 would result in a diminished throughput
(26kHz maximum conversion rate). The method described
in Figure 7 could not be used because time t
25
would be
violated. The approach in Figure 8 results in an improved
throughput rate (33kHz maximum with a 1µs clock) and
DATACLK is LOW during t
25
.
COMPATIBILITY WITH THE ADS7813
The only difference between the ADS7812 and the ADS7813
is in the internal control logic and the digital interface. Since
the ADS7813 is a 16-bit converter, the internal shift register
is 16 bits wide. In addition, only 16-bit decisions are made
during the conversion. Thus, the ADS7813’s conversion
time is approximately 133% of the ADS7812’s.
The timing presented in this data sheet will allow as much
compatibility as possible with the ADS7813. The main
concern will be the different number of serial clocks. If a
design must be compatible with both the ADS7812 and
ADS7813, it is recommended to consider the ADS7813
first. If the design works with the ADS7813, it will certainly
work with the ADS7812. This is also true in regards to
layout (see the Layout section of this data sheet).
CHIP SELECT (CS)
The CS input allows the digital outputs of the ADS7812 to
be disabled and gates the external DATACLK signal when
EXT/INT is HIGH. See Figure 9 for the enable and disable
time associated with CS and Figure 3 for a block diagram of
the ADS7812’s logic. The digital outputs can be disabled at
any time.
Note that a conversion is initiated on the falling edge of CONV
even if CS is HIGH. If the EXT/INT input is LOW (internal
DATACLK) and CS is HIGH during the entire conversion, the
previous conversion result will be lost (the serial transmission
occurs but DATA and DATACLK are disabled).
TABLE IV. Complete List of Ideal Input Ranges.
ANALOG CONNECT CONNECT CONNECT INPUT
INPUT R1
IN
R2
IN
R3
IN
IMPEDANCE
RANGE (V) TO TO TO (kΩ) COMMENT
0.3125 to 2.8125 V
IN
V
IN
V
IN
> 10,000 Specified offset and gain
–0.417 to 2.916 V
IN
V
IN
BUF 26.7 V
IN
cannot go below GND – 0.3V
0.417 to 3.750 V
IN
V
IN
GND 26.7 Offset and gain not specified
±3.333 V
IN
BUF V
IN
21.3 Specified offset and gain
–15 to 5 V
IN
BUF BUF 45.7 Offset and gain not specified
±10 V
IN
BUF GND 45.7 Specified offset and gain
0.833 to 7.5 V
IN
GND V
IN
21.3 Offset and gain not specified
–2.5 to 17.5 V
IN
GND BUF 45.7 Exceeds absolute maximum V
IN
2.5 to 22.5 V
IN
GND GND 45.7 Exceeds absolute maximum V
IN
0 to 2.857 BUF V
IN
V
IN
45.7 Offset and gain not specified
–1 to 3 BUF V
IN
BUF 21.3 V
IN
cannot go below GND – 0.3V
0 to 4 BUF V
IN
GND 21.3 Specified offset and gain
–6.25 to 3.75 BUF BUF V
IN
26.7 Offset and gain not specified
0 to 10 BUF GND V
IN
26.7 Specified offset and gain
0.357 to 3.214 GND V
IN
V
IN
45.7 Offset and gain not specified
–0.5 to 3.5 GND V
IN
BUF 21.3 V
IN
cannot go below GND – 0.3V
0.5 to 4.5 GND V
IN
GND 21.3 Specified offset and gain
±5 GND BUF V
IN
26.7 Specified offset and gain
1.25 to 11.25 GND GND V
IN
26.7 Offset and gain not specified
ANALOG INPUT
The ADS7812 offers a number of input ranges. This is
accomplished by connecting the three input resistors to
either the analog input (V
IN
), to ground (GND), or to the
2.5V reference buffer output (BUF). Table I shows the
input ranges that are typically used in data acquisition
applications. These ranges are all specified to meet the
specifications given in the Specifications table. Table IV
contains a complete list of ideal input ranges, associated
input connections, and comments regarding the range.
ActiveHI-Z HI-Z
BUSY, DATA,
DATACLK
(1)
CS
t
27
t
26
NOTE: (1) DATACLK is an output only when EXT/INT is LOW.
FIGURE 9. Enable and Disable Timing for Digital Outputs.