Datasheet

ADS7807
12
SBAS022D
www.ti.com
FIGURE 6. Conversion and Read Timing with External Clock ( EXT/INT tied HIGH) Read During a Conversion.
EXTERNAL DATA CLOCK
(During a Conversion)
After conversion ‘n’ has been initiated, valid data from con-
version ‘n – 1’ can be read and will be valid up to 12µs after
the start of conversion ‘n’. Do not attempt to clock out data
from 12µs after the start of conversion ‘n’ until
BUSY (pin 24)
rises; this will result in data loss. NOTE: For the best possible
performance when using an external data clock, data should
not be clocked out during a conversion. The switching noise
of the asynchronous data clock can cause digital feedthrough
degrading the converter’s performance. Refer to Table V and
Figure 6.
TAG FEATURE
TAG (pin 20) inputs serial data synchronized to the external
or internal data clock.
When using an external data clock, the serial bit stream input
on TAG will follow the LSB output on SDATA until the internal
output register is updated with new conversion results. See
Table V and Figures 5 and 6.
The logic level input on TAG for the first rising edge of the
internal data clock will be valid on SDATA after all 16 bits of
valid data have been output.
INPUT RANGES
The ADS7807 offers three input ranges: standard ±10V and
0V-5V, and a 0V-4V range for complete, single-supply sys-
tems. See Figures 7a and 7b for the necessary circuit
connections for implementing each input range and optional
offset and gain adjust circuitry. Offset and full-scale error
(1)
specifications are tested with the fixed resistors, see Figure
7b. Adjustments for offset and gain are described in the
Calibration section of this data sheet.
The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors compen-
sate for this adjustment and can be left out if the offset and
gain will be corrected in software (refer to the Calibration
section).
The input impedance, summarized in Table II, results from
the combination of the internal resistor network (see the front
page of this product data sheet) and the external resistors
used for each input range (see Figure 8). The input resistor
divider network provides inherent over-voltage protection to
at least ±5.5V for R2
IN
and ±12V for R1
IN
.
Analog inputs above or below the expected range will yield
either positive full-scale or negative full-scale digital outputs,
respectively. Wrapping or folding over for analog inputs
outside the nominal range will not occur.
NOTE: (1) Full-scale error includes offset and gain errors measured at both
+FS and –FS.
EXTERNAL
DATACLK
CS
Bit 15 (MSB)
R/C
BUSY
DATA
TAG
Bit 0 (LSB) Tag 0 Tag 1
Tag 1 Tag 16 Tag 17 Tag 18 Tag 0
t
20
t
21
t
1
t
11
t
3
t
17
t
18
t
19
t
22
t
20