Datasheet

ADS7807
11
SBAS022D
www.ti.com
FIGURE 5. Conversion and Read Timing with External Clock ( EXT/INT Tied HIGH) Read after Conversion.
FIGURE 4. Serial Data Timing Using Internal Data Clock (TAG tied LOW).
0
Bit 15 (MSB)
1 2 3 4 16 17 18
Bit 14 Bit 1
Bit 0 (LSB)
Tag 0
Tag 1
Tag 1
Tag 2 Tag 15 Tag 16
Tag 17 Tag 18
Tag 0
t
20
t
21
t
21
t
3
t
17
t
18
t
19
t
20
t
22
t
1
EXTERNAL
DATACLK
CS
R/C
BUSY
SDATA
TAG
1
MSB Valid
CS or R/C
(1)
DATACLK
SDATA
BUSY
t
7
+ t
8
t
16
t
15
t
14
t
13
2 3 15 16
Bit 14 Valid Bit 1 ValidBit 13 Valid LSB Valid
1
MSB Valid
2
Bit 14 Valid
(Results from previous conversion.)
NOTE: (1) If controlling with
CS
, tie
R/C
LOW. Data bus pins will remain Hi-Z at all times.
If controlling with
R/C
, tie
CS
LOW. Data bus pins will be active when
R/C
is HIGH, and should be left unconnected.