Datasheet

ADS7807
10
SBAS022D
www.ti.com
INTERNAL DATA CLOCK
(During a Conversion)
To use the internal data clock, tie EXT/INT (pin 8) LOW. The
combination of
R/C (pin 22) and CS (pin 23) LOW will initiate
conversion ‘n’ and activate the internal data clock (typically
900kHz clock rate). The ADS7807 will output 16 bits of valid
data, MSB first, from conversion ‘n-1’ on SDATA (pin 19),
synchronized to 16 clock pulses output on DATACLK (pin 18).
The data will be valid on both the rising and falling edges of the
internal data clock. The rising edge of
BUSY (pin 24) can be
used to latch the data. After the 16th clock pulse, DATACLK will
remain LOW until the next conversion is initiated, while SDATA
will go to whatever logic level was input on TAG (pin 20) during
the first clock pulse. Refer to Table V and Figure 4.
EXTERNAL DATA CLOCK
To use an external data clock, tie EXT/INT (pin 8) HIGH. The
external data clock is not a conversion clock; it can only be
used as a data clock. To enable the output mode of the
ADS7807,
CS (pin 23) must be LOW and R/C (pin 22) must
be HIGH. DATACLK must be HIGH for 20% to 70% of the
total data clock period; the clock rate can be between DC and
10MHz. Serial data from conversion ‘n’ can be output on
SDATA (pin 19) after conversion ‘n’ is completed or during
conversion ‘n + 1’.
An obvious way to simplify control of the converter is to tie
CS LOW and use R/C to initiate conversions.
While this is perfectly acceptable, there is a possible problem
when using an external data clock. At an indeterminate point
from 12µs after the start of conversion ‘n’ until
BUSY rises,
the internal logic will shift the results of conversion ‘n’ into the
output register. If
CS is LOW, R/C HIGH, and the external
clock is HIGH at this point, data will be lost. So, with
CS
LOW, either R/C and/or DATACLK must be LOW during this
period to avoid losing valid data.
EXTERNAL DATA CLOCK
(After a Conversion)
After conversion ‘n’ is completed and the output registers
have been updated,
BUSY (pin 24) will go HIGH. With CS
LOW and R/C HIGH, valid data from conversion ‘n’ will be
output on SDATA (pin 19) synchronized to the external data
clock input on DATACLK (pin 18). The MSB will be valid on
the first falling edge and the second rising edge of the
external data clock. The LSB will be valid on the 16th falling
edge and 17th rising edge of the data clock. TAG (pin 20) will
input a bit of data for every external clock pulse. The first bit
input on TAG will be valid on SDATA on the 17th falling edge
and the 18th rising edge of DATACLK; the second input bit
will be valid on the 18th falling edge and the 19th rising edge,
etc. With a continuous data clock, TAG data will be output on
SDATA until the internal output registers are updated with
the results from the next conversion. Refer to Table V and
Figure 5.
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
1
Convert Pulse Width 0.04 12 µs
t
2
(1)
Data Valid Delay after
R/C
LOW 18 20 µs
t
3
(1)
BUSY
Delay from
Start of Conversion 12 85 ns
t
4
(1)
BUSY
LOW 18 20 µs
t
5
BUSY
Delay after 90 ns
End of Conversion
t
6
Aperture Delay 40 ns
t
7
(1)
Conversion Time 18 20 µs
t
8
(1)
Acquisition Time 5 7 µs
t
9
Bus Relinquish Time 10 83 ns
t
10
BUSY
Delay after Data Valid 20 60 ns
t
11
(1)
Previous Data Valid 12 18 µs
after Start of Conversion
t
12
(1)
Bus Access Time and BYTE Delay 10 83 ns
t
13
(1)
Start of Conversion 2.4 µs
to DATACLK Delay
t
14
(1)
DATACLK Period 0.6 0.82 0.85 µs
t
15
(1)
Data Valid to DATACLK 150 200 ns
HIGH Delay
t
16
(1)
Data Valid after DATACLK 150 200 ns
LOW Delay
t
17
External DATACLK Period 100 ns
t
18
External DATACLK LOW 40 ns
t
19
External DATACLK HIGH 50 ns
t
20
CS
and
R/C
to External 25 ns
DATACLK Setup Time
t
21
R/C
to
CS
Setup Time 10 ns
t
22
(1)
Valid Data after DATACLK HIGH 2 12 ns
t
7
+ t
8
Throughput Time 25 µs
DIP (NT) PACKAGE ONLY TIMING
t
2
Data Valid Delay after
R/C
LOW 19 20 µs
t
3
BUSY
Delay from 85 ns
Start of Conversion
t
4
BUSY
LOW 19 20 µs
t
7
Conversion Time 19 20 µs
t
8
Acquisition Time 5 µs
t
11
Previous Data Valid 12 19 µs
after Start of Conversion
t
12
Bus Access Time and BYTE Delay 83 ns
t
13
Start of Conversion 1.4 µs
to DATACLK Delay
t
14
DATACLK Period 1.1 µs
t
15
Data Valid to DATACLK 20 75 ns
HIGH Delay
t
16
Data Valid after DATACLK 400 600 ns
LOW Delay
t
22
Valid Data after DATACLK HIGH 25 ns
NOTE: (1) See the bottom part of this table if using the DIP (NT) package.
TABLE V. Conversion and Data Timing. T
A
= –40°C to +85°C.
SERIAL OUTPUT
Data can be clocked out with the internal data clock or an
external data clock. When using serial output, be careful with
the parallel outputs, D7-D0 (pins 9-13 and 15-17), as these
pins will come out of Hi-Z state whenever
CS (pin 23) is LOW
and
R/C (pin 22) is HIGH. The serial output can not be tri-
stated and is always active. Refer to the Applications
Information section for specific serial interfaces.