Datasheet

ADS7806
9
SBAS021B
www.ti.com
PARALLEL OUTPUT (AFTER A CONVERSION)
After conversion ‘n’ is completed and the output registers
have been updated,
BUSY (pin 24) will go HIGH. Valid data
from conversion ‘n’ will be available on D7-D0 (pins 9-13 and
15-17).
BUSY going high can be used to latch the data. Refer
to Table V and Figures 2 and 3 for timing constraints.
PARALLEL OUTPUT (DURING A CONVERSION)
After conversion ‘n’ has been initiated, valid data from conver-
sion ‘n – 1’ can be read and will be valid up to 12µs after the
start of conversion ‘n’. Do not attempt to read data beyond
12µs after the start of conversion ‘n’ until
BUSY (pin 24) goes
HIGH; this may result in reading invalid data. Refer to Table V
and Figures 2 and 3 for timing constraints.
prior to reading the same data on the serial port, but data
cannot be read through the serial port prior to reading the
same data on the parallel port.
PARALLEL OUTPUT
To use the parallel output, tie EXT/INT (pin 8) HIGH and
DATACLK (pin 18) LOW. SDATA (pin 19) should be left
unconnected. The parallel output will be active when
R/C
(pin 22) is HIGH and CS (pin 23) is LOW. Any other
combination of
CS and R/C will tri-state the parallel output.
Valid conversion data can be read in two 8-bit bytes on D7-
D0 (pins 9-13 and 15-17). When BYTE (pin 21) is LOW, the
eight most significant bits will be valid with the MSB on D7.
When BYTE is HIGH, the four least significant bits will be
valid with the LSB on D4. BYTE can be toggled to read both
bytes within one conversion cycle.
Upon initial power up, the parallel output will contain indeter-
minate data.
FIGURE 2. Conversion Timing with Parallel Output ( CS and DATACLK tied LOW, EXT/INT tied HIGH).
FIGURE 3. Using
CS to Control Conversion and Read Timing with Parallel Outputs.
t
10
BUSY
R/C
MODE
Acquire
Convert
t
11
t
7
t
6
t
3
t
4
t
1
Acquire Convert
t
8
t
6
t
3
Parallel
Data Bus
Previous
High Byte Valid
t
12
Hi-Z Not Valid
t
2
t
9
High Byte
Valid
t
12
t
9
t
12
BYTE
t
1
Previous Low
Byte Valid
Previous High
Byte Valid
Low Byte
Valid
High Byte
Valid
t
12
Hi-Z
t
12
t
12
t
5
Hi-Z State
BUSY
R/C
DATA
BUS
High Byte
t
3
t
4
t
21
t
21
t
1
t
21
t
21
BYTE
t
21
t
21
t
21
t
21
t
21
t
21
Hi-Z State Low Byte Hi-Z State
t
9
t
12
t
9
t
12
CS