Datasheet
ADS7806
18
SBAS021B
www.ti.com
In addition, CPOL and CPHA should be set to zero (SCK
normally LOW and data captured on the rising edge). The
command control byte for the 8-bit transfer should be set to
20
H
and for the 12-bit transfer to 61
H
.
SPI™ INTERFACE
The SPI interface is generally only capable of 8-bit data
transfers. For some microcontrollers with SPI interfaces, it
might be possible to receive data in a similar manner as
shown for the QSPI interface in Figure 12. The microcontroller
will need to fetch the eight most significant bits before the
contents are overwritten by the least significant bits.
A modified version of the QSPI interface, see Figure 13,
might be possible. For most microcontrollers with SPI inter-
face, the automatic generation of the start-of-conversion
pulse will be impossible and will have to be done with
software. This will limit the interface to ‘DC’ applications due
to the insufficient jitter performance of the convert pulse tself.
DSP56000 INTERFACING
The DSP56000 serial interface has an SPI compatibility
mode with some enhancements. Figure 14 shows an inter-
face between the ADS7806 and the DSP56000 which is very
similar to the QSPI interface seen in Figure 12. As mentioned
in the QSPI section, the DSP56000 must be programmed to
enable the interface when a LOW-to-HIGH transition on SC1
is observed (
BUSY
going HIGH at the end of conversion).
The DSP56000 can also provide the convert pulse by includ-
ing a monostable multi-vibrator as seen in Figure 15. The
receive and transmit sections of the interface are decoupled
(asynchronous mode) and the transmit section is set to
generate a word length frame sync every other transmit
frame (frame rate divider set to two). The prescale modulus
should be set to five.
The monostable multi-vibrator in this circuit will provide
varying pulse widths for the convert pulse. The pulse width
will be determined by the external R and C values used with
the multi-vibrator. The 74HCT123N data sheet shows that
the pulse width is (0.7)RC. Choosing a pulse width as close
to the minimum value specified in this data sheet will offer the
best performance. See the Starting A Conversion section of
this data sheet for details on the conversion pulse width.
The maximum conversion rate for a 20.48MHz DSP56000 is
35.6kHz. If a slower oscillator can be tolerated on the
DSP56000, a conversion rate of 40kHz can be achieved by
using a 19.2MHz clock and a prescale modulus of four.
FIGURE 15. DSP56000 Interface to the ADS7806. Processor initiates conversions.
FIGURE 14. DSP56000 Interface to the ADS7806.
SPI is a registered trademark of Motorola.
R/C
BUSY
SDATA
DATACLK
CS
EXT/INT
BYTE
ADS7806
SC1
SRD
SCO
DSP56000
SYN = 0 (Asychronous)
GCK = 1 (Gated clock)
SCD1 = 0 (SC1 is an input)
SHFD = 0 (Shift MSB first)
WL1 = 0 WL0 = 1 (Word length = 12 bits)
Convert Pulse
R
EXT1
C
EXT1
Q1
B1
CLR1
A1
R/C
DATACLK
SDATA
CS
EXT/INT
BYTE
ADS7806
74HCT123N
SC2
SC0
SRD
DSP56000
SYN = 0 (Asychronous)
GCK = 1 (Gated clock)
SCD2 = 1 (SC2 is an output)
SHFD = 0 (Shift MSB first)
WL1 = 0 WL0 = 1 (Word length = 16 bits)
R
+5V
C
+5V