Datasheet

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Low-Power 12-Bit Sampling CMOS

ANALOG-to-DIGITAL CONVERTER

DESCRIPTION

The ADS7806 is a low-power, 12-bit, sampling Analog-to-

Digital (A/D) converter using state of the art CMOS structures.

It contains a complete 12-bit, capacitor-based, Successive

Approximation Register (SAR) A/D converter with sample-

and-hold, clock, reference, and a microprocessor interface with

parallel and serial output drivers.

The ADS7806 can acquire and convert to full 12-bit accuracy

in 25µs max, while consuming only 35mW max. Laser

trimmed scaling resistors provide standard industrial input

ranges of ±10V and 0V to +5V. In addition, a 0V to +4V range

allows development of complete single-supply systems.

The ADS7806 is available in a 0.3" DIP-28 and SO-28, both

fully specified for operation over the industrial –40°C to

+85°C temperature range.

FEATURES

● POWER DISSIPATION: 35mW max

● POWER-DOWN MODE: 50µW

● ACQUISITION AND CONVERSION: 25µs max

● ±1/2 LSB MAX INL AND DNL

● 72dB MIN SINAD WITH 1kHz INPUT

● INPUT RANGES:

10V, 0V to +5V, and 0V TO +4V

● SINGLE +5V SUPPLY OPERATION

● PARALLEL AND SERIAL DATA OUTPUT

● PIN-COMPATIBLE WITH THE 16-BIT ADS7807

● USES INTERNAL OR EXTERNAL REFERENCE

● 0.3" DIP-28 AND SO-28

ADS7806

SBAS021B – NOVEMBER 1992 – REVISED SEPTEMBER 2003

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

ADS7806

CDAC

6kΩ

40kΩ

10kΩ

BUSY

Parallel

and

Serial

Data

Out

Comparator

Buffer

20kΩ

REF

Successive Approximation Register and Control Logic

Clock

Power

Down

BYTE

R/C

40kΩ

Internal

+2.5V Ref

Reference

Power-Down

Serial Data

Clock

Parallel Data

CAP

Serial Data

All trademarks are the property of their respective owners.

Summary of content (25 pages)

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ADS7806 ADS 780 6 ADS 780 6 SBAS021B – NOVEMBER 1992 – REVISED SEPTEMBER 2003 Low-Power 12-Bit Sampling CMOS ANALOG-to-DIGITAL CONVERTER FEATURES DESCRIPTION ● ● ● ● ● ● ● ● ● ● ● The ADS7806 is a low-power, 12-bit, sampling Analog-toDigital (A/D) converter using state of the art CMOS structures.
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ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) Analog Inputs: R1IN ............................................................................ ±12V R2IN ........................................................................... ±5.5V CAP ................................... VANA + 0.3V to AGND2 – 0.3V REF .......................................... Indefinite Short to AGND2, Momentary Short to VANA Ground Voltage Differences: DGND, AGND1, and AGND2 ............. ±0.3V VANA ................
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ELECTRICAL CHARACTERISTICS (Cont.) At TA = –40°C to +85°C, fS = 40kHz, VDIG = VANA = +5V, and using internal reference and fixed resistors (see Figure 7b), unless otherwise specified.
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PIN DESCRIPTIONS DIGITAL I/O PIN # NAME 1 2 3 4 5 6 7 8 9 R1IN AGND1 R2IN CAP REF AGND2 SB/BTC EXT/INT D7 10 11 12 13 14 15 16 17 18 19 20 21 22 D6 D5 D4 D3 DGND D2 D1 D0 DATACLK SDATA TAG BYTE R/C O O O I/O O I I I 23 CS I 24 BUSY O 25 26 27 28 PWRD REFD VANA VDIG I I DESCRIPTION Analog Input. See Figure 7. Analog Sense Ground Analog Input. See Figure 7. Reference Buffer Output. 2.2µF tantalum capacitor to ground. Reference Input/Output. 2.2µF tantalum capacitor to ground.
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TYPICAL CHARACTERISTICS TA = +25°C, fS = 40kHz, VDIG = VANA = +5V, and using internal reference and fixed resistors (see Figure 7b), unless otherwise specified.
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TYPICAL CHARACTERISTICS (Cont.) TA = +25°C, fS = 40kHz, VDIG = VANA = +5V, and using internal reference and fixed resistors (see Figure 7b), unless otherwise specified. POWER-SUPPLY RIPPLE SENSITIVITY INL/DNL DEGRADATION PER LSB OF P-P RIPPLE 1 Linearity Degradation (LSB/LSB) 12-Bit (LSBs) 0.10 0 All Codes INL –0.10 12-Bit (LSBs) 0.10 0 –0.
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BASIC OPERATION PARALLEL OUTPUT Figure 1a shows a basic circuit to operate the ADS7806 with a ±10V input range and parallel output. Taking R/C (pin 22) LOW for 40ns (12µs max) will initiate a conversion. BUSY (pin 24) will go LOW and stay LOW until the conversion is completed and the output register is updated. If BYTE (pin 21) is LOW, the eight Most Significant Bits (MSBs) will be valid when BUSY rises; if BYTE is HIGH, the four Least Significant Bits (LSBs) will be valid when BUSY rises.
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The ADS7806 will begin tracking the input signal at the end of the conversion. Allowing 25µs between convert commands assures accurate acquisition of a new signal. Refer to Tables II and III for a summary of CS , R/C, and BUSY states, and Figures 2 through 6 for timing diagrams. CS R/C BUSY 1 X X OPERATION None. Databus is in Hi-Z state. ↓ 0 1 Initiates conversion ‘n’. Databus remains in Hi-Z state. 0 ↓ 1 Initiates conversion ‘n’. Databus enters Hi-Z state. 0 1 ↑ Conversion ‘n’ completed.
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prior to reading the same data on the serial port, but data cannot be read through the serial port prior to reading the same data on the parallel port. PARALLEL OUTPUT To use the parallel output, tie EXT/INT (pin 8) HIGH and DATACLK (pin 18) LOW. SDATA (pin 19) should be left unconnected. The parallel output will be active when R/C (pin 22) is HIGH and CS (pin 23) is LOW. Any other combination of CS and R/C will tri-state the parallel output.
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SYMBOL DESCRIPTION t1 Convert Pulse Width t2 Data Valid Delay after R/C LOW t3 BUSY Delay from INTERNAL DATA CLOCK MIN TYP MAX UNITS 0.04 14.7 12 µs 20 µs 85 ns 20 µs (During A Conversion) To use the internal data clock, tie EXT/INT (pin 8) LOW. The combination of R/C (pin 22) and CS (pin 23) LOW will initiate conversion ‘n’ and activate the internal data clock (typically a 900kHz clock rate).
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FIGURE 5. Conversion and Read Timing with External Clock (EXT/INT Tied HIGH) Read after Conversion. ADS7806 SBAS021B www.ti.
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EXTERNAL DATA CLOCK TAG FEATURE (After a Conversion) TAG (pin 20) inputs serial data synchronized to the external or internal data clock. After conversion ‘n’ is completed and the output registers have been updated, BUSY (pin 24) will go HIGH. With CS LOW and R/C HIGH, valid data from conversion ‘n’ will be output on SDATA (pin 19) synchronized to the external data clock input on DATACLK (pin 18). The MSB will be valid on the first falling edge and the second rising edge of the external data clock.
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each input range (see Figure 8). The input resistor divider network provides inherent over-voltage protection to at least ±12V on R1IN and ±5.5V on R2IN. Analog inputs above or below the expected range will yield either positive full-scale or negative full-scale digital outputs, respectively. There will be no wrapping or folding over for analog inputs outside the nominal range. GAIN ADJUST RANGE (mV) ±10V ±15 ±60 0 to 5V ±4 ±30 0 to 4V ±3 ±30 TABLE VI.
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ered when choosing the accuracy and drift specifications of the external resistors. In most applications, 1% metal-film resistors will be sufficient. The external resistors, see Figure 7b, may not be necessary in some applications. These resistors provide compensation for an internal adjustment of the offset and gain which allows calibration with a single supply. Not using the external resistors will result in offset and gain errors in addition to those listed in the electrical characteristics section.
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200Ω 39.8kΩ VIN CDAC (High Impedance) (0.3125V to 2.8125V) 66.5kΩ 40kΩ 20kΩ 9.9kΩ +5V 100Ω +2.5V +2.5V 200Ω 39.8kΩ CDAC (High Impedance) (0.3125V to 2.8125V) 33.2kΩ 100Ω 20kΩ 9.9kΩ 40kΩ VIN +2.5V 200Ω +2.5V 39.8kΩ VIN CDAC (High Impedance) (0.3125V to 2.8125V) 33.2kΩ 100Ω 40kΩ 20kΩ 9.9kΩ +2.5V +2.5V FIGURE 9. Circuit Diagrams Showing External and Internal Resistors.
PAGE 16
cycle. This capacitor also provides compensation for the output of the buffer. Using a capacitor any smaller than 1µF can cause the output buffer to oscillate and may not have sufficient charge for the CDAC. Capacitor values larger than 2.2µF will have little affect on improving performance. See Figures 10 and 11. 7000 6000 5000 REFD HIGH will power-down the internal 2.5V reference. All other analog circuitry, including the reference buffer, will be active.
PAGE 17
on the ADS7806 is approximately 5% to 10% of the amount on similar A/D converters with the charge redistribution Digital-to-Analog Converter (DAC) CDAC architecture. There is also a resistive front end which attenuates any charge which is released. The end result is a minimal requirement for the drive capability on the signal conditioning preceding the A/D converter. Any op amp sufficient for the signal in an application will be sufficient to drive the ADS7806.
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In addition, CPOL and CPHA should be set to zero (SCK normally LOW and data captured on the rising edge). The command control byte for the 8-bit transfer should be set to 20H and for the 12-bit transfer to 61H. Convert Pulse DSP56000 ADS7806 SPI™ INTERFACE R/C The SPI interface is generally only capable of 8-bit data transfers. For some microcontrollers with SPI interfaces, it might be possible to receive data in a similar manner as shown for the QSPI interface in Figure 12.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS7806U/1K SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 ADS7806UB/1K SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7806U/1K SOIC DW 28 1000 367.0 367.0 55.0 ADS7806UB/1K SOIC DW 28 1000 367.0 367.0 55.
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