Datasheet
ADS7805
8
SBAS020D
www.ti.com
FIGURE 2. Bit Locations Relative to State of BYTE (pin 23).
DIGITAL OUTPUT
BINARY TWO’S COMPLEMENT
DESCRIPTION ANALOG INPUT BINARY CODE HEX CODE
Full-Scale Range ±10V
Least Significant 305µV
Bit (LSB)
+Full Scale 9.999695V 0111 1111 1111 1111 7FFF
(10V – 1LSB)
Mid-scale 0V 0000 0000 0000 0000 0000
One LSB below –305µV 1111 1111 1111 1111 FFFF
Mid-scale
–Full Scale –10V 1000 0000 0000 0000 8000
Table III. Ideal Input Voltages and Output Codes.
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
1
Convert Pulse Width 40 7000 ns
t
2
Data Valid Delay after R/C LOW 8 µs
t
3
BUSY Delay from R/C LOW 65 ns
t
4
BUSY LOW 8 µs
t
5
BUSY Delay after 220 ns
End of Conversion
t
6
Aperture Delay 40 ns
t
7
Conversion Time 7.6 8 µs
t
8
Acquisition Time 2 µs
t
9
Bus Relinquish Time 10 35 83 ns
t
10
BUSY Delay after Data Valid 50 200 ns
t
11
Previous Data Valid 7.4 µs
after R/C LOW
t
7
+ t
6
Throughput Time 9 10 µs
t
12
R/C to CS Setup Time 10 ns
t
13
Time Between Conversions 10 µs
t
14
Bus Access Time 10 83 ns
and BYTE Delay
TABLE IV. Conversion Timing.
Bit 0 (LSB)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 15 (MSB)
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
6
7
8
9
10
11
12
13
14
23
22
21
20
19
18
17
16
15
ADS7805
BYTE LOW
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15 (MSB)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
6
7
8
9
10
11
12
13
14
23
22
21
20
19
18
17
16
15
ADS7805
BYTE HIGH
+5V
READING DATA
The ADS7805 outputs full or byte-reading parallel data in
Binary Two’s Complement data output format. The parallel
output will be active when R/C (pin 24) is HIGH and CS (pin
25) is LOW. Any other combination of CS and R/C will tri-
state the parallel output. Valid conversion data can be read
in a full parallel, 16-bit word or two 8-bit bytes on pins 6-13
and pins 15-22. BYTE (pin 23) can be toggled to read both
bytes within one conversion cycle. Refer to Table III for ideal
output codes and Figure 2 for bit locations relative to the
state of BYTE.
PARALLEL OUTPUT (After a Conversion)
After conversion ‘n’ is completed and the output registers
have been updated, BUSY (pin 26) will go HIGH. Valid data
from conversion ‘n’ will be available on D15-D0 (pins 6-13
and 15-22). BUSY going HIGH can be used to latch the data.
Refer to Table IV and Figures 3 to 5 for timing specifications.
PARALLEL OUTPUT (During a Conversion)
After conversion ‘n’ has been initiated, valid data from con-
version ‘n – 1’ can be read and will be valid up to 7µs after
the start of conversion ‘n’. Do not attempt to read data from
7µs after the start of conversion ‘n’ until BUSY (pin 26) goes
HIGH; this may result in reading invalid data. Refer to Table
IV and Figures 3 to 5 for timing specifications.
Note! For the best possible performance, data should not be
read during a conversion. The switching noise of the asyn-
chronous data transfer can cause digital feedthrough de-
grading the converter’s performance.
The number of control lines can be reduced by tying CS LOW
while using R/C to initiate conversions and activate the
output mode of the converter (see Figure 3).