Datasheet

ADS7805
4
SBAS020D
www.ti.com
1V
IN
Analog Input. See Figure 7.
2 AGND1 Analog Ground. Used internally as ground reference point.
3 REF Reference Input/Output. 2.2µF tantalum capacitor to ground.
4 CAP Reference Buffer Capacitor. 2.2µF tantalum capacitor to ground.
5 AGND2 Analog Ground
6 D15 (MSB) O Data Bit 15. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.
7 D14 O Data Bit 14. Hi-Z state when CS is HIGH, or when R/C is LOW.
8 D13 O Data Bit 13. Hi-Z state when CS is HIGH, or when R/C is LOW.
9 D12 O Data Bit 12. Hi-Z state when CS is HIGH, or when R/C is LOW.
10 D11 O Data Bit 11. Hi-Z state when CS is HIGH, or when R/C is LOW.
11 D10 O Data Bit 10. Hi-Z state when CS is HIGH, or when R/C is LOW.
12 D9 O Data Bit 9. Hi-Z state when CS is HIGH, or when R/C is LOW.
13 D8 O Data Bit 8. Hi-Z state when CS is HIGH, or when R/C is LOW.
14 DGND Digital Ground
15 D7 O Data Bit 7. Hi-Z state when CS is HIGH, or when R/C is LOW.
16 D6 O Data Bit 6. Hi-Z state when CS is HIGH, or when R/C is LOW.
17 D5 O Data Bit 5. Hi-Z state when CS is HIGH, or when R/C is LOW.
18 D4 O Data Bit 4. Hi-Z state when CS is HIGH, or when R/C is LOW.
19 D3 O Data Bit 3. Hi-Z state when CS is HIGH, or when R/C is LOW.
20 D2 O Data Bit 2. Hi-Z state when CS is HIGH, or when R/C is LOW.
21 D1 O Data Bit 1. Hi-Z state when CS is HIGH, or when R/C is LOW.
22 D0 (LSB) O Data Bit 0. Least Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.
23 BYTE I Selects 8 most significant bits (LOW) or 8 least significant bits (HIGH).
24 R/C I With CS LOW and BUSY HIGH, a Falling Edge on R/C Initiates a new conversion. With CS LOW, a rising edge on R/C
enables the parallel output.
25 CS I Internally OR’d with R/C. If R/C LOW, a falling edge on CS initiates a new conversion.
26 BUSY O At the start of a conversion, BUSY goes LOW and stays LOW until the conversion is completed and the digital outputs
have been updated.
27 V
ANA
Analog Supply Input. Nominally +5V. Decouple to ground with 0.1µF ceramic and 10µF tantalum capacitors.
28 V
DIG
Digital Supply Input. Nominally +5V. Connect directly to pin 27. Must be ≤ V
ANA
.
DIGITAL
PIN # NAME I/O DESCRIPTION
TABLE I. Pin Assignments.
PIN CONFIGURATION
V
DIG
V
ANA
BUSY
CS
R/C
BYTE
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
V
IN
AGND1
REF
CAP
AGND2
D15 (MSB)
D14
D13
D12
D11
D10
D9
D8
DGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS7805