Datasheet

ADS7800
9
SBAS001A
www.ti.com
FIGURE 7. Read Mode: R/C Pulse HIGH— Outputs Enabled Only When R/C is High.
SYMBOL PARAMETER MIN TYP MAX UNITS
t
W
R/C Pulse Width 40 10 ns
t
DBC
BUSY delay from R/C 80 150 ns
t
B
BUSY LOW 2.5 2.7 µs
t
AP
Aperture Delay 13 ns
∆t
AP
Aperture Jitter 150 ps, rms
t
C
Conversion Time 2.47 2.70 µs
t
DBE
BUSY from End of Conversion 100 ns
t
DB
BUSY Delay after Data Valid 25 75 200 ns
t
A
Acquisition Time 130 300 ns
t
A
+t
C
Throughput Time 2.6 3.0 µs
t
HDR
Valid Data Held After R/C LOW 20 50 ns
t
S
CS or HBE LOW before R/C Falls 25 5 ns
t
H
CS or HBE LOW after R/C Falls 25 0 ns
t
DD
Data Valid from CS LOW, R/C HIGH, and HBE in Desired State (Load = 100pF) 65 150 ns
t
HDR
Valid Data Held After R/C Low 20 50 ns
t
HL
Delay to Hi-Z State after R/C Falls or CS Rises (3kΩ Pullup or Pulldown) 50 150 ns
TABLE III. Timing Specifications (T
MIN
to T
MAX
).
Pin 24 may be slightly more sensitive than pin 23 to supply
variations, but to maintain maximum system accuracy, both
should be well isolated from digital supplies with wide load
variations.
To limit the effects of digital switching elsewhere in a
system on the analog performance of the system, it often
makes sense to run a separate +5V supply conductor from
the supply regulator to any analog components requiring
+5V, including the ADS7800.
The V
S
pins (23 and 24) should be connected together and
bypassed with a parallel combination of a 6.8µF tantalum
capacitor and a 0.1µF ceramic capacitor located close to the
converter to obtain noise-free operation. (See Figure 2.) The
–V
S
pin 22 should be bypassed with a 1µF tantalum
capacitor, again as close as possible to the ADS7800.
Noise on the power supply lines can degrade converter
performance, especially noise and spikes from a switching
power supply. Appropriate supplies or filters must be used.
The GND pins (4 and 13) are also separated internally, and
should be directly connected to a ground plane under the
FIGURE 8. Conversion Start Timing.
R/C
Converter
Mode
BUSY
Acquire Convert Acquire Convert
Data
Valid
Hi-Z State
Data
BUS
Hi-Z StateHi-Z State
Data
Valid
t
HDR
and t
HL
t
C
t
AP
t
DBE
t
DD
t
DBC
t
W
t
B
t
A
t
AP
CS or
HBE
R/C
BUSY
t
S
t
H
t
W
t
DBC
Data
Bus
Hi-Z StateData Valid
t
HDR
and t
HL