Datasheet

ADS7279/80
#1
SDI
SDO
ADS7279/80
#2
SDI
SDO
ADS7279/80
#3
SDI
SDO
MicroController
SDISDOGPIO1 GPIO2 GPIO3
Programdevice#1CFR_D[7:5]=XX0b
INT
CS
CONVST
CS
CONVST
CS
CONVST
EOC/INT
CDI CDI
Programdevice#2and#3CFR_D[7:5]=XX1b
SCLK
SCLKSCLK SCLK
READResult
EOC#1
(activelow)
Common
CONVST
F / #S 1CS
INT
(activelow)
Common SCLK
CascadedManualTr Samplinigger/ReadWhile g
(UseinternalCCLK,EOC,and programmedasactivelow)
heldlowduringtheNtimes16bitstransfercycle
INT
CS
SDO#2
SDI
t
CONV
=18CCLKs
EO
S
1……………………16
1101b
READResult
1……………………16
EOC
Nth
1……………………16
EOS
1101b
READResult
FS/ #2
CS
FS/ #3CS
SDO#1
Nthfrom #1
SDO#3
Nthfrom #2
Nthfrom #3
Nthfrom #1
Nthfrom #1Nthfrom #2
t
4
t
4
1101b
t
SAMPLE1
=3CCLKsMin
ADS7279
ADS7280
SBAS436A – MAY 2008 – REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com
Figure 61. Multiple Converters Connected Using Chain Mode
When multiple converters are used in daisy-chain mode, the first converter is configured in regular mode while
the other converters are configured in chain mode. When a converter is configured in chain mode, the CDI input
data go straight to the output register; therefore, the serial input data passes through the converter with a 16
SCLK (if the TAG feature is disabled) or a 24 SCLK delay, as long as CS is active. Figure 62 shows a detailed
timing diagram. In this timing, the conversions in each converter are performed simultaneously.
Figure 62. Simplified Cascade Mode Timing with Shared CONVST and Continuous CS
Care must be given to handle the multiple CS signals when the converters operate in daisy-chain mode. The
different chip select signals must be low for the entire data transfer (in this example, 48 bits for three converters).
The first 16-bit word after the falling chip select is always the data from the chip that received the chip select
signal.
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