Datasheet

REFERENCE
CONVERTER OPERATION
OSC
Divider
1/2
= 1
= 0
Conversion Clock
(CCLK)
CFR_D10
SPI Serial
Clock (SCLK)
Manual Channel Select Mode
ADS7279
ADS7280
www.ti.com ............................................................................................................................................................... SBAS436A – MAY 2008 – REVISED JUNE 2009
The ADS7279/80 must operate with an external reference with a range from 0.3V to 5V. A clean, low-noise,
well-decoupled reference voltage on the REF+ pin is required to ensure good converter performance. A
low-noise bandgap reference such as the REF5040 can be used to drive this pin. A 22 µ F ceramic decoupling
capacitor is required between the REF+ and REF – pins of the converter. These capacitors should be placed as
close as possible to the device pins. REF – should be connected with an own via to the analog ground plane with
the shortest possible distance. A series resistor between the reference and the REF50xx is neither required
(because the REF50xx is capable of driving a 22 µ F capacitor while maintaining stability) nor recommended (as a
result of additional nonlinearity); see also Figure 68 .
The ADS7279/80 has an oscillator that is used as an internal clock, which controls the conversion rate. The
frequency of this clock is 21MHz (minimum). The oscillator is always on, unless the device is in the deep
power-down state or the device is programmed for using SCLK as the conversion clock (CCLK). The minimum
acquisition (sampling) time takes 3 CCLKs (equivalent to 143ns at 21MHz) and the conversion time takes 18
conversion clocks (CCLK) or approximately 857ns at 21MHz to complete one conversion.
The conversion can also be programmed to run based on an external serial clock, SCLK. This option allows the
designer to fully synchronize the converter with the system. The serial clock SCLK is first reduced to 1/2 of its
frequency before it is used as the conversion clock (CCLK). For example, with a 42MHz SCLK, this reduction
provides a 21MHz clock for conversions. If it is desired to start a conversion at a specific rising edge of SCLK
when the external SCLK is programmed as the source of the conversion clock (and manual conversion start is
selected), the setup time between CONVST and that rising SCLK edge should be observed. This configuration
ensures that the conversion is complete in 18 CCLKs (or 36 SCLKs). The minimum setup time is 20ns to ensure
synchronization between CONVST and SCLK. In many cases, the conversion can start one SCLK period (or
CCLK) later, which results in a conversion length of 19 CCLKs (or 37 SCLKs). The 20ns setup time is not
required if the synchronization is not critical to the application.
The duty cycle of SCLK is not critical as long as it meets the minimum high and low time requirements of 8ns.
The ADS7279/80 is designed for high-speed applications; therefore, a higher serial clock (SCLK) must be
supplied to be able to sustain the high throughput with the serial interface. As a result, the clock period of SCLK
must be at most 1 µ s (when used as the conversion clock, CCLK). The minimum clock frequency is also
governed by the parasitic leakage of the capacitive digital-to-analog (CDAC) capacitors internal to the
ADS7279/80.
Figure 56. Converter Clock
The conversion cycle starts with selecting an acquisition channel by writing a channel number to the command
register, CMR. The command length can be as short as four SCLKs.
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