Datasheet
TIMING CHARACTERISTICS
(1) (2)
: 5V
ADS7229
ADS7230
SBAS437A – MAY 2008 – REVISED JUNE 2009 ...............................................................................................................................................................
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All specifications typical at – 40 ° C to +85 ° C and +VA = +VBD = 5V, unless otherwise noted.
ADS7229, ADS7230
PARAMETER MIN TYP MAX UNIT
External,
0.5 21
f
CCLK
= 1/2 f
SCLK
f
CCLK
Frequency, conversion clock, CCLK MHz
Internal,
21 23 24.5
f
CCLK
= 1/2 f
SCLK
t
1
Setup time, falling edge of CS to EOC 1 CCLK
t
2
Hold time, falling edge of CS to EOC 0 ns
t
CL
Pulse duration, CONVST low 40 ns
t
3
Hold time, falling edge of CS to EOS 20 ns
t
4
Setup time, rising edge of CS to EOS 20 ns
t
5
Hold time, rising edge of CS to EOS 20 ns
Setup time, falling edge of CS to first falling
t
6
5 ns
SCLK
t
SCLKL
Pulse duration, SCLK low 8 t
SCLK
– 8 ns
t
SCLKH
Pulse duration, SCLK high 8 t
SCLK
– 8 ns
I/O clock only 20
I/O and conversion clock 23.8 2000
t
SCLK
Cycle time, SCLK ns
I/O clock, chain mode 20
I/O and conversion clock,
23.8 2000
chain mode
t
H2
Hold time, falling edge of SCLK to SDO invalid 10pF load 2 ns
t
D1
Delay time, falling edge of SCLK to SDO valid 10pF load 10 ns
Delay time, falling edge of CS to SDO valid,
t
D2
10pF load 8.5 ns
SDO MSB output
t
S1
Setup time, SDI to falling edge of SCLK 8 ns
t
H1
Hold time, SDI to falling edge of SCLK 4 ns
Delay time, rising edge of CS/FS to SDO t
D3
t
D3
5 ns
3-state
Setup time, 16th falling edge of SCLK before
t
7
10 ns
rising edge of CS/FS
(1) All input signals are specified with t
r
= t
f
= 1.5ns (10% to 90% of VBD) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2) See timing diagrams.
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