Datasheet

EOC#1
(activelow)
CONVST #2=1
FS/ #1CS
INT
(activelow)
Common S KCL
C sa c da ed M na ual Tr aig hge Wr/Read ile S mpling
(UseinternalCCLK,EOC,and programmedasactivelow)
heldlowduringtheNtimes16bitstransfercycle
INT
CS
SDO#2
SDI
t
CONV
=18CCLKs
EOS
1……………………16
1101b
READResult
1……………………16
EOC
Nth
1……………………16
EOS
1101b
READResult
FS/ #2CS
FS/ #3CS
SDO#1
Nthfrom #1
SDO#3
N 1th#- 2
Nthfrom #3
Nthfrom #1
Nthfrom #1
N 1th#- 2
t
4
t
4
CONVST #1
CONVST #3
READResult
1101b
t
SAMPLE1
=3CCL nKsMi
ADS7229
ADS7230
SBAS437A – MAY 2008 – REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com
Figure 64 shows a slightly different scenario where CONVST is not shared by the second converter. Converters
#1 and #3 have the same CONVST signal. In this case, converter #2 simply passes the previous conversion data
downstream.
Figure 64. Simplified Cascade Timing (Separate CONVST)
The number of SCLKs required for a serial read cycle depends on the combination of different read modes, TAG
bit, chain mode, and the way a channel is selected (that is, auto channel select). These possible configurations
are listed in Table 6 .
Table 6. Required SCLKs For Different Read Out Mode Combinations
CHAIN MODE AUTO CHANNEL NUMBER OF SCLK PER SPI
ENABLED CFR.D5 SELECT CFR.D11 TAG ENABLED CFR.D1 READ TRAILING BITS
0 0 0 12 None
0 0 1 ≥ 17 MSB is TAG bit plus zero(s)
0 1 0 12 None
0 1 1 ≥ 17 TAG bit plus seven zeros
1 0 0 16 None
1 0 1 24 TAG bit plus seven zeros
1 1 0 16 None
1 1 1 24 TAG bit plus seven zeros
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