Datasheet

EOC#1
(activelow)
Common CONVST
FS/ #1CS
INT
(activelow)
Common SCLK
C dasca e nua amp ind a lT S lM rigg /ReadWhile er g
(UseinternalCCLK,EOC,and programmedasactivelow)INT
SDO#2
SDI
t =
CONV
18CCLKs
EOS
1……………………16
1101b
READResult
1……………………16
EOC
Nth
1……………………16
EO
S
1101b
R ReEAD sult
FS/ #2CS
SDO#1
N froth m #1
SDO#3
N froth m #2
N froth m #3
N froth m #1
N froth m #3N froth m #3
N froth m #1
N froth m #1 N froth m #1
t
4
t
4
FS/ #3CS
t
4
READResult
1101b
t
SAMPLE1
=3CCLKsMin
ADS7229
ADS7230
www.ti.com ............................................................................................................................................................... SBAS437A – MAY 2008 – REVISED JUNE 2009
Case 1: If chip select is not toggled ( CS stays low), the next 16 bits are data from the upstream converter, and so
on. This configuration is shown in Figure 62 . If there is no upstream converter in the chain, as with converter #1
in the example, the same data from the converter are going to be shown repeatedly.
Case 2: If the chip select is toggled during a chain mode data transfer cycle, as illustrated in Figure 63 , the same
data from the converter are read out again and again in all three discrete 16-bit cycles. This result is not a
desired outcome.
Figure 63. Simplified Cascade Mode Timing with Shared CONVST and Discrete CS
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