Datasheet
Configuring the Converter and Default Mode
READING THE CONFIGURATION REGISTER
READING CONVERSION RESULT
ADS7229
ADS7230
SBAS437A – MAY 2008 – REVISED JUNE 2009 ...............................................................................................................................................................
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The converter can be configuring with command 1110b (write to the CFR) or command 1111b (default mode). A
write to the CFR requires a 4-bit command followed by 12 bits of data. A 4-bit command takes effect at the fourth
falling edge of SCLK. A CFR write takes effect at the 16th falling edge of SCLK.
A default mode command can be achieved by simply tying SDI to +VBD. As soon as the chip is selected, at least
four '1's are clocked in by SCLK. The default value of the CFR is loaded into the CFR at the fourth falling edge of
SCLK.
CFR default values are all 1s (except for CFR_D1 on the ADS7229; this bit is ignored by the device and is
always read as a '0'). The same default values apply for the CFR after a power-on reset (POR) and software
reset.
The host processor can read back the value programmed in the CFR by issuing command 1100b. The timing is
similar to reading a conversion result, except that CONVST is not used and there is no activity on the EOC/ INT
pin. The CFR value read back contains the first four MSBs of conversion data plus valid 12-bit CFR contents.
Table 4 shows the Configuration Register Map.
Table 4. Configuration Register (CFR) Map
SDI BIT
CFR - D[11 - 0] DEFINITION
Channel select mode
D11 default = 1
0: Manual channel select enabled. Use channel select commands to 1: Auto channel select enabled. All channels are sampled and
access a different channel. converted sequentially until the cycle after this bit is set to 0.
Conversion clock (CCLK) source select
D10 default = 1
0: Conversion clock (CCLK) = SCLK/2 1: Conversion clock (CCLK) = Internal OSC
Trigger (conversion start) select: start conversion at the end of sampling (EOS). If D9 = 0, the D4 setting is ignored.
D9 default = 1
0: Auto trigger automatically starts (4 internal clocks after EOC inactive) 1: Manual trigger manually started by falling edge of CONVST
D8 default = 1 Don't care Don't care
Pin 10 polarity select when used as an output (EOC/ INT)
D7 default = 1
0: EOC Active high / INT active high 1: EOC active low / INT active low
Pin 10 function select when used as an output (EOC/ INT)
D6 default = 1
0: Pin used as INT 1: Pin used as EOC
Pin 10 I/O select for chain mode operation
D5 default = 1
0: Pin 10 is used as CDI input (chain mode enabled) 1: Pin 10 is used as EOC/ INT output
Auto nap power-down enable/disable (mid voltage and comparator shut down between cycles). This bit setting is ignored if D9 = 0.
D4 default = 1
0: Auto nap power-down enabled (not activated) 1: Auto nap power-down disabled
Nap power-down (mid voltage and comparator shut down between cycles). This bit is set to 1 automatically by wake-up command.
D3 default = 1
0: Enable/activate device in nap power-down 1: Remove device from nap power-down (resume)
Deep power-down. This bit is set to 1 automatically by wake-up command.
D2 default = 1
0: Enable/activate device in deep power-down 1: Remove device from deep power-down (resume)
D1 default = TAG bit enable. This bit is ignored by the ADS7229 and is always read 0.
0: ADS7229
0: TAG bit disabled. 1: TAG bit output enabled. TAG bit appears at the 17th SCLK.
1: ADS7230
Reset
D0 default = 1
0: System reset 1: Normal operation
The conversion result is available to the input of the output data register (ODR) at EOC and presented to the
output of the output register at the next falling edge of CS or FS. The host processor can then shift the data out
via the SDO pin any time except during the quiet zone. This quite zone is 20ns before and 20ns after the end of
sampling (EOS) period. In the quiet zone the FS/CS should be high, to avoid performance loss when switching
from sampling-mode to hold-mode. End of sampling (EOS) is defined as the falling edge of CONVST when
manual trigger is used or the end of the third conversion clock (CCLK) after EOC if auto trigger is used.
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