Datasheet

DIGITAL INTERFACE
Internal Register
WRITING TO THE CONVERTER
ADS7229
ADS7230
www.ti.com ............................................................................................................................................................... SBAS437A – MAY 2008 – REVISED JUNE 2009
The serial clock is designed to accommodate the latest high-speed processors with an SCLK frequency up to
50MHz. Each cycle starts with the falling edge of FS/ CS. The internal data register content that is made available
to the output register at the EOC (presented on the SDO output pin at the falling edge of FS/ CS) is the MSB.
Output data are valid at the falling edge of SCLK with a t
d(SCLKF-SDOVALID)
delay so that the host processor can
read it at the falling edge. Serial data input is also read at the falling edge of SCLK.
The complete serial I/O cycle starts with the first falling edge of SCLK after the falling edge of FS/ CS and ends
16 falling edges of SCLK later (see NOTE). The serial interface is very flexible. It works with CPOL = 0 , CPHA =
1 or CPOL = 1, CPHA = 0. This flexibility means the falling edge of FS/ CS may fall while SCLK is high. The
same relaxation applies to the rising edge of FS/ CS where SCLK may be high or low as long as the last SCLK
falling edge occurs before the rising edge of FS/ CS.
NOTE:
There are cases where a cycle is 4 SCLKs or up to 24 SCLKs depending on the read
mode combination. See Table 3 and Table 6 for details.
The internal register consists of two parts, 4 bits for the command register (CMR) and 12 bits for configuration
data register (CFR).
Table 3. Command Set Defined by Command Register (CMR)
(1)
WAKE-UP FROM MINIMUM SCLKs
D[15:12] HEX COMMAND D[11:0] AUTO NAP REQUIRED R/W
0000b 0h Select analog input channel 0
(2)
Don't care Y 4 W
0001b 1h Select analog input channel 1
(2)
Don't care Y 4 W
0010b 2h Don't care Don't care – – –
0011b 3h Don't care Don't care – – –
0100b 4h Don't care Don't care – – –
0101b 5h Don't care Don't care – – –
0110b 6h Don't care Don't care – – –
0111b 7h Don't care Don't care – – –
1000b 8h Reserved for factory test, don't use Reserved – – –
1001b 9h Reserved for factory test, don't use Reserved – – –
1010b Ah Reserved for factory test, don't use Reserved – – –
1011b Bh Wake up Don't care Y 4 W
1100b Ch Read CFR Don't care – 16 R
1101b Dh Read data Don't care – 12 R
1110 Eh Write CFR CFR value – 16 W
1111b Fh Default mode (load CFR with default value) Don't care Y 4 W
(1) When SDO is not in 3-state mode (FS/ CS low), the bits from SDO are always part of a conversion result (depending on how many
SCLKs are supplied).
(2) These two commands apply to the ADS7230 only.
There are two different types of writes to the register, a 4-bit write to the CMR and a full 16-bit write to the CMR
plus CFR. The command set is listed in Table 3 . A simple command requires only 4 SCLKs and the write takes
effect at the fourth falling edge of SCLK. A 16-bit write or read takes at least 16 SCLKs (see Table 6 for
exceptions that require more than 16 SCLKs).
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