Datasheet

Power-Down Modes
SettlingTime(ns)
+V
ASupplyCurrent(mA)
100
10
1
0.1
0 10000 40000
20000 30000
ADS7229
ADS7230
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............................................................................................................................................................... SBAS437A MAY 2008 REVISED JUNE 2009
The ADS7229/30 has a comprehensive, built-in power-down feature. There are three power-down modes: Deep
power-down mode, Nap power-down mode, and Auto nap power-down mode. All three power-down modes are
enabled by setting the related CFR bits. The first two power-down modes are activated when enabled. A wakeup
command, 1011b, resumes device operation from a power-down mode. Auto nap power-down mode works
slightly differently. When the converter is enabled in Auto nap power-down mode, an end of conversion instance
(EOC) puts the device into auto nap power-down. The beginning of sampling resumes converter operation. The
contents of the configuration register are not affected by any of the power-down modes. Any ongoing conversion
when nap or deep power-down is activated is aborted.
Figure 57. Typical Analog Supply Current Drop versus Time After Power-Down
Deep Power-Down Mode
Deep power-down mode can be activated by writing to configuration register bit CFR_D2. When the device is in
Deep power-down mode, all blocks except the interface are in power-down. The external SCLK is blocked to the
analog block. The analog blocks no longer have bias currents and the internal oscillator is turned off. In this
mode, supply current falls from 5.7mA to 4nA in 100ns. The wake-up time after a deep power-down is 1 µ s.
When bit D2 in the configuration register is set to '0', the device is in Deep power-down. Setting this bit to '1' or
sending a wake-up command resumes the converter operation from the Deep power-down state.
Nap Mode
In Nap mode, the ADS7229/30 turns off biasing of the comparator and the mid-voltage buffer. In this mode,
supply current falls from 5.7mA in normal mode to about 0.3mA in 200ns after the configuration cycle. The
wake-up (resume) time from Nap power-down mode is 3 CCLKs (143ns with a 21MHz conversion clock). As
soon as the CFR_D3 bit in the control register is set to '0', the device goes into Nap power-down mode,
regardless of the conversion state. Setting this bit to '1' or sending a wake-up command resumes converter
operation from the Nap power-down state.
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Product Folder Link(s): ADS7229 ADS7230