Datasheet

THEORY OF OPERATION
ANALOG INPUT
DeviceinHoldMode
AGND
150W
+IN
-IN
AGND
+VA
150W
4pF
4pF
40pF
40pF
ADS7229
ADS7230
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The ADS7229 and ADS7230 are two high-speed, low power, successive approximation register (SAR)
analog-to-digital converters (ADCs) that use an external reference. The architecture is based on charge
redistribution, which inherently includes a sample-and-hold function.
These devices have an internal clock that is used to run the conversion; these devices can also be programmed
to run the conversion based on the external serial clock, SCLK.
The ADS7229 has one analog input. The analog input is provided to two input pins: +IN and – IN. When a
conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a
conversion is in progress, both +IN and – IN inputs are disconnected from any internal function.
The ADS7230 has two inputs. Both inputs share the same common pin, COM. The negative input is the same as
the – IN pin for the ADS7229. The ADS7230 can be programmed to select a channel manually or can be
programmed into the auto channel select mode to sweep between channel 0 and channel 1 automatically.
Throughout this document, the term ADS7229/30 refers to both devices, unless specifically noted otherwise.
When the converter enters before hold mode, the voltage difference between the +IN and – IN inputs is captured
on the internal capacitor array. The voltage on the – IN input is limited between AGND – 0.2V and AGND + 0.2V,
allowing the input to reject small signals that are common to both the +IN and – IN inputs. The +IN input has a
range of – 0.2V to (V
REF
+ 0.2V). The input span [(+IN) – ( – IN)] is limited to 0V to V
REF
.
The (peak) input current through the analog inputs depends upon a number of factors: sample rate, input
voltage, and source impedance. The current into the ADS7229/30 charges the internal capacitor array during the
sample period. After this capacitance has been fully charged, there is no further input current. The source of the
analog input voltage must be able to charge the input capacitance (45pF) to a 12-bit settling level within the
minimum acquisition time (120ns). When the converter goes into hold mode, the input impedance is greater than
1G Ω .
Care must be taken regarding the absolute analog input voltage. To maintain linearity of the converter, the +IN
and – IN inputs and the span [(+IN) – ( – IN)] should be within the limits specified. Outside of these ranges,
converter linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass
filters should be used. Care should be taken to ensure that the output impedance of the sources driving the +IN
and – IN inputs are matched. If this input matching is not observed, the two inputs could have different settling
times. This difference may result in an offset error, gain error, and linearity errors that change with temperature
and input voltage.
Figure 53. Input Equivalent Circuit
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Product Folder Link(s): ADS7229 ADS7230