Datasheet

CHB1P/CHB3
CHB1N/CHB2
CHB0P/CHB1
CHB0N/CHB0
CHA1P/CHA3
CHA1N/CHA2
CHA0P/CHA1
CHA0N/CHA0
SDOB
BUSY
CLOCK
CS
RD
CONVST
SDI
M0
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
ADS8363
ADS7263
ADS7223
(Thermal Pad)
CMB
CMA
AGND
AVDD
DGND
DVDD
NC
SDOA
32
REFIO1
9
31
REFIO2
10
30
RGND
11
29
AGND
12
28
AVDD
13
27
NC
14
26
NC
15
25
M1
16
ADS8363
ADS7263
ADS7223
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SBAS523B OCTOBER 2010REVISED JANUARY 2011
PIN CONFIGURATION
RHB PACKAGE
QFN-32
(TOP VIEW)
Pin Descriptions
PIN
NAME NO. TYPE
(1)
DESCRIPTION
CHB1P/CHB3 1 AI Fully-differential noninverting analog input channel B1 or pseudo-differential input B3
CHB1N/CHB2 2 AI Fully-differential inverting analog input channel B1 or pseudo-differential input B2
CHB0P/CHB1 3 AI Fully-differential noninverting analog input channel B0 or pseudo-differential input B1
CHB0N/CHB0 4 AI Fully-differential inverting analog input channel B0 or pseudo-differential input B0
CHA1P/CHA3 5 AI Fully-differential noninverting analog input channel A1 or pseudo-differential input A3
CHA1N/CHA2 6 AI Fully-differential inverting analog input channel A1 or pseudo-differential input A2
CHA0P/CHA1 7 AI Fully-differential nonInverting analog input channel A1 or pseudo-differential input A1
CHA0N/CHA0 8 AI Fully-differential inverting analog input channel A1 or pseudo-differential input A0
REFIO1 9 AIO Reference voltage input/output 1. A ceramic capacitor of 22µF connected to RGND is required.
REFIO2 10 AIO Reference voltage input/output 2. A ceramic capacitor of 22µF connected to RGND is required.
RGND 11 P Reference ground. Connect to analog ground plane with a dedicated via.
AGND 12, 30 P Analog ground. Connect to analog ground plane.
AVDD 13, 29 P Analog power supply, 2.7V to 5.5V. Decouple to AGND with a 1mF ceramic capacitor.
14,
NC NC This pin is not internally connected.
15, 26
M1 16 DI Mode pin 1. Selects the digital output mode (see Table 4).
M0 17 DI Mode pin 0. Selects analog input channel mode (see Table 4).
Serial data input. This pin is used to set up of the internal registers, and can also be used in
SDI 18 DI
ADS8361-compatible manner. The data on SDI are ignored when CS is high.
Conversion start. The ADC switches from sample into hold mode on the rising edge of CONVST.
CONVST 19 DI
Thereafter, the conversion starts with the next rising edge of the CLOCK pin.
Read data. Synchronization pulse for the SDOx outputs and SDI input. RD only triggers when CS is
RD 20 DI
low.
(1) AI = analog input, AIO = analog input/output, DI = digital input, DO = digital output, DIO = digital input/output, P = power supply, NC =
not connected.
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Product Folder Link(s): ADS8363 ADS7263 ADS7223