Datasheet

ADS8363
ADS7263
ADS7223
www.ti.com SBAS523B –OCTOBER 2010–REVISED JANUARY 2011
LAYOUT for the entire printed circuit board (PCB) or a
dedicated analog ground area may be used. In case
For optimum performance, care should be taken with
of a separated analog ground area, ensure a
the physical layout of the ADS8363/7263/7223
low-impedance connection between the analog and
circuitry, particularly if the device is used at the
digital ground of the ADC by placing a bridge
maximum throughput rate. In this case, it is
underneath (or next) to the ADC (see Figure 44).
recommended to have a fixed phase relationship
Otherwise, even short undershoots on the digital
between CLOCK and CONVST.
interface with a value of less than –300mV can lead
to conduction of ESD diodes, causing current flow
Additionally, the high-performance SAR architecture
through the substrate and degrading the analog
is sensitive to glitches or sudden changes on the
performance.
power supply, reference, ground connections, and
digital inputs that occur just before latching the output
During the layout of the PCB, care should be taken to
of the internal analog comparator. Therefore, during
avoid any return currents crossing any sensitive
an operation of an n-bit SAR converter, there are n
analog areas or signals. No signal must exceed the
windows in which large external transient voltages
limit of –300mV with respect to the corresponding
(glitches) can affect the conversion result. Such
(AGND or DGND) ground plane.
glitches might originate from switching power
supplies, nearby digital logic, or high-power devices.
SUPPLY
The degree of impact depends on the reference
voltage, layout, and the actual timing of the external
The ADS8363/7263 has two separate supplies: the
event.
DVDD pin for the buffers of the digital interface and
the AVDD pin for all the remaining circuits.
With this possibility in mind, power to the device
should be clean and well-bypassed. A 1µF ceramic
DVDD can range from 2.3V to 5.5V, allowing the
bypass capacitor should be placed at each supply pin
ADC to easily interface with processors and
(connected to the corresponding ground pin) as close
controllers. To limit the injection of noise energy from
to the device as possible.
external digital circuitry, DVDD should be properly
filtered. A bypass capacitor of 1µF should be placed
If the reference voltage is external, the operational
between the DVDD pin and the digital ground plane.
amplifier should be able to drive the 22µF capacitor
without oscillation. A series resistor between the
AVDD supplies the internal analog circuitry. For
driver output and the capacitor may be required. To
optimum performance, a linear regulator (for
minimize any code-dependent voltage drop on this
example, the UA7805 family) is recommended to
path, a small value should be used for this resistor
generate the analog supply voltage in the range of
(10Ω max). TI's REF50xx family is able to directly
2.7V to 5.5V for the ADC and the necessary analog
drive such a capacitive load.
front-end.
Bypass capacitors of 1µF should be connected to the
GROUNDING
analog ground plane such that the current is allowed
The AGND, RGND, and DGND pins should be to flow through the pad of these capacitors (that is,
connected to a clean ground reference. All the vias should be placed on the opposite side of the
connections should be kept as short as possible to connection between the capacitor and the
minimize the inductance of these paths. It is power-supply pin of the ADC).
recommended to use vias connecting the pads
directly to the ground plane. In designs without
DIGITAL INTERFACE
ground planes, the ground trace should be kept as
To further optimize performance of the device, a
wide as possible. Avoid connections that are close to
series resistor of between 10Ω to 100Ω can be used
the grounding point of a microcontroller or digital
on each digital pin of the device. In this way, the slew
signal processor.
rate of the input and output signals is reduced,
Depending on the circuit density of the board,
limiting the noise injection from the digital interface.
placement of the analog and digital components, and
the related current loops, a single solid ground plane
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