Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal VQFN 32

f =

-3dB

ln(2) 2×

2 20tp

CLK

ADS8363

ADS7263

ADS7223

SBAS523B –OCTOBER 2010–REVISED JANUARY 2011

www.ti.com

SDI versus A0

• A software change to setup internal reference

DAC1 properly through SDI while removing the

Pin 18 (SDI) of the ADS8363/7263/7223 is used to

external resistors; or

update the internal registers, whereas on the

• An additional external buffer between the resistor

ADS8361, pin 18 (A0) is used in conjunction with M0

divider and the required 22µF (min) capacitor on

to select the input channel.

the REFIO1 input.

If, in an existing design, the ADS8361 is used in

In the latter case, while the capacitor stabilizes the

two-channel mode (M0 = '0') and the status of the A0

reference voltage during the entire conversion, the

pin is unchanged within the first four clock cycles

buffer must recharge it by providing an average

after issuing a conversion start (rising edge of

current only; thus, the required minimum bandwidth of

CONVST), the ADS8363/7263/7223 act similarly to

the buffer can be calculated using Equation 4:

the ADS8361 and convert either channels CHx0 (if

SDI is held low during the entire period) or channels

CHx1 (if SDI is held high during the entire period).

(4)

Figure 37 shows the behavior of the

ADS8363/7263/7223 in such a situation.

The buffer must also be capable of driving the 22µF

load while maintaining its stability.

The ADS8363/7263/7223 can be also be used to

replace the ADS8361 when run in four-channel mode

Timing

(M0 = '1'). In this case, the A0 pin is held static (high

or low), which is also required in for the SDI pin to

In half-clock mode (default), the ADS8363/7263/7223

prevent accidental update of the SDI register.

family of devices provides the conversion delay after

completion of the conversion (see Figure 1), while the

In both cases described above, the additional

ADS8361 offers the conversion result during the

features of the ADS8363/7263/7223

conversion process.

(pseudo-differential input mode, programmable

reference voltage output, and the various

power-down modes) cannot be accessed, but the

hardware and software would remain

The ADS8363/7263/7223 output the first bit with the

backward-compatible to the ADS8361.

falling edge of the RD input. The ADS8361 starts the

data transfer with the first falling edge of the clock if

Internal Reference

RD is high.

The internal reference of the ADS8361 delivers 2.5V

If the ADS8363/7263/7223 operate with half-clock

(typ) after power up, while the reference output of the

timing in modes II and IV, the RD input should not be

ADS8363/7263/7223 is powered down by default. In

held high longer than one clock cycle to ensure

this case, the unbuffered reference input has a

proper function of the data output SDOA.

code-dependent input impedance, while the

ADS8361 offers a high-impedance (buffered)

CONVST

reference input. If an existing ADS8361-based design

If the ADS8363/7263/7223 operate with half-clock

uses the internal reference of the device and relies on

timing in modes II and IV, the CONVST input must

an external resistor divider to adjust the input voltage

not be held high longer than one clock cycle to

range of the ADC, migration to the ADS8363 family

ensure proper function of the device.

requires one of the following conditions:

Product Folder Link(s): ADS8363 ADS7263 ADS7223