Datasheet
C
H
x
C
H
x
C
H
x
C
H
x
C
H
x
C
H
x
1
20
CLOCK
CONVST
and RD
SDI
CONVST
and RD
R[1:0] = ‘01’ CR update
→
A[3:0] = ‘x010’ REFDAC1
update
→
1
20
RPD = ‘1’ REFDAC1
enabled
→
20
1
20
1
SDI
(Write)
C
1
12-bit data
DAC settings
R[1:0] = ‘01’ CR update
→
A[3:0] = ‘0011’ read
REFDAC1
→
12-bit REFDAC1
register contents
R[1:0] = ‘01’ CR update→
A[3:0] = x010’ REFDAC1 update→
RPD = ‘1’ REFDAC1 enabled→
20
1
SDOA
(1)
16-bit data n 1-
CHAx
16-bit REFDAC1
register content
C
H
x
16-bit data n
CHAx
16-bit data n + 1
CHAx
ignored
SDOA
(1)
R[1:0] = ‘01’ CR update
→
A[3:0] = ‘0011’ read REFDAC1→
16-bit data n
CHAx
16-bit REFDAC1
register content
SDI
(Read)
ignored
new settings
BUSY
conversion n conversion n + 1 conversion n + 2 conversion n + 3 conversion n + 4
16-bit data n + 3
CHAx
BUSY
conversion n conversion n + 1 conversion n + 2
Full-Clock Mode
Half-Clock Mode
CID = ‘0’
C
0
S
R
F
C
P
D
E
C
I
D
C
E
C
1
C
0
S
R
F
C
P
D
E
C
I
D
C
E
C
H
x
C
1
C
0
S
R
F
C
P
D
E
C
I
D
C
E
C
1
C
0
S
R
F
C
P
D
E
C
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D
C
E
ADS8363
ADS7263
ADS7223
www.ti.com
SBAS523B –OCTOBER 2010–REVISED JANUARY 2011
PROGRAMMING THE REFERENCE DAC When channel information is enabled (CID = '0'), the
first two bits of the data output contain the currently
The internal reference DACs can be set by issuing an
selected analog input channel indicator ('0' for CHx0
RD pulse while providing an control word with R[1:0]
or '1' for CHx1), followed by the 16-bit DAC register
= '01' and A[3:0] = 'X010' or 'X101', depending on
contents and an additional '00'. While the register
which DAC is going to be updated. Thereafter, a
contents are valid on SDOA, the conversion result of
second RD pulse must be generated with a control
channel Ax is lost (if a conversion was performed in
word that starts with the first five bits being ignored
parallel), the conversion result of channel Bx is valid
followed by the reference power control and the
on SDOB (if enabled), and data on SDI are ignored,
corresponding 10-bit DAC value (refer to Figure 40).
as shown in Figure 40).
To verify the DACs settings, an RD pulse must be
The default value of the DAC registers after power-up
generated while providing a control word containing
is 7FFh, corresponding to a disabled reference
R[1:0] = '01' and A[3:0] = '0011' or '0110' to initialize
voltage of 2.5V on both REFIOx pins.
the read access of the appropriate DAC register.
Triggering the RD line again causes the SDOA output
to provide the 16-bit DAC register value followed by
'0000', if channel information is disabled (CID = '1').
Figure 40. DAC Register Write and Read Access Timing
(Both SDOx Active and CID = '0')
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