Datasheet
A
D
x
C
H
x
A
D
x
C
H
x
A
D
A
C
H
0
A
D
B
C
H
0
A
D
A
C
H
1
A
D
B
C
H
0
A
D
A
C
H
0
1
20
CLOCK
CONVST
and RD
SDI
SDOA
(1)
SDOB
(1)
BUSY
16-bit data 2n -
CHAx
High-Z
1
1
20
conversion n 1-
of both CHxx
16-bit data n
CHA0
16-bit data n
CHB0
conversion n
of both CH 0x
16-bit data n + 1
CHA1
conversion n + 1
of both CH 1x
20
1
20
1
16-bit data 1n -
CHBx
20
1
C[1:0] are ignored
R[1:0] = ‘11’ no update
→
C[1:0] are ignored
R[1:0] = ‘00’ no update
→
C[1:0] are ignored
R[1:0] = ‘01’ register update
→
→
SR = ‘1’
Auto-Sleep Mode
SDOA
(1)
SDOB
(1)
16-bit data n
CHB0
16-bit data n
CHA0
High-Z
A
D
x
C
H
x
n 2 16-bit-
data CHBx
16-bit data 2n -
CHAx
16-bit data 1n -
CHBx
A
D
x
16-bit data 2n -
CHBx
C
H
x
A
D
x
C
H
x
A
D
x
C
H
x
no conversion,
read access only
no conversion,
read access only
ADS8363
ADS7263
ADS7223
SBAS523B –OCTOBER 2010–REVISED JANUARY 2011
www.ti.com
Special Mode IV (Half-Clock Mode Only)
If auto-sleep power-down mode is enabled, the
conversion results are presented during the next
As with Special Mode II, these devices also offer a
conversion, as shown in Figure 39.
special read mode for Mode IV, where both data
results of a conversion can be read by triggering a
This mode can be used for fully- or
single RD pulse (refer to Figure 39). Additionally, in
pseudo-differential inputs (note that in
this case, the SR bit in the CONFIG register must be
pseudo-differential mode, the sequencer is used to
set to '1' while the CONVST and RD pins can still be
control the input multiplexer); channel information is
tied together, but are issued every 40 CLOCK cycles
available if CID = '0' in fully-differential mode only
instead of 20. The RD signal in this mode must not
(CID forced to '1' in pseudo-differential mode).
be longer than one clock cycle to avoid corruption of
The internal FIFO is available in this mode; when
output data.
used, a single read pulse allows for reading of all
Data are available on the SDOA pin, accordingly.
stored conversion data. The FIFO should be
completely filled when used for the first time in order
to ensure proper functionality.
(1) ADS7263/7223 output data with the MSB located as ADS8363 and the last 2/4 bits being '0'.
Figure 39. Special Read Mode IV Timing
(M0 = '1', M1 = '1', PDE = '0', SR = '1', CID = '0', Fully-Differential Example)
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