Datasheet

A
D
B
A
D
A
A
D
x
1
20
CLOCK
CONVST
and RD
SDI
SDOA
(1)
SDOB
(1)
BUSY
16-bit data 2n -
CHAx
C[1:0] = ‘00’ → CH 0 nextx
R[1:0] = ‘01’ → register update
→ SR = ‘1’
no conversion,
read access only
High-Z
1
1
20
A
D
x
16-bit data 2n -
CHBx
conversion n-1
of both CHxx
16-bit data n
CHA0
A
D
A
16-bit data n
CHB0
conversion n
of both CH 0x
16-bit data n + 1
CHA1
conversion n + 1
of both CH 1x
no conversion,
read access only
C[1:0] = ‘11’ CH 1 next→ x
R[1:0] = ‘11’ no update→
C[1:0] = ‘00’ CH 0 nextx→
R[1:0] = ‘00’ no update→
20
1
20
1
16-bit data n 1-
CHBx
A
D
x
20
1
ADS8363
ADS7263
ADS7223
www.ti.com SBAS523B –OCTOBER 2010–REVISED JANUARY 2011
Special Read Mode II (Half-Clock Mode Only)
The RD signal in this mode must not be longer than
one clock cycle to avoid corruption of output data.
For Mode II, a special read mode is available in the
ADS8363/7263/7223 where both data results can be
This special mode can be used for fully- or
read out triggered by a single RD pulse (refer to
pseudo-differential inputs. Channel information is
Figure 36). To activate this mode, The SR bit in the
valid in fully-differential mode only if CID = '0' (it
CONFIG register must be set to '1' (see Table 6). The
contains correct ADC information while the channel
CONVST and RD pins can still be tied together but
bit is invalid in pseudo-differential mode). Note that
are issued every 40 CLOCK cycles instead of 20.
FIFO is not available in this mode.
Output data are presented on SDOA only while
SDOB is held in 3-state.
(1) ADS7263/7223 output data with the MSB located as ADS8363 and the last 2/4 bits being '0'.
Figure 36. Special Read Mode II Timing Diagram
(M0 = '0', M1 = '1', PDE = '0', SR = '1', CID = '0', Fully-Differential Example)
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