Datasheet

1
20
CLOCK
CONVST
andRD
SDI
SDOA
(1)
BUSY
CHA0
C[1:0]= ‘00’ CH 0/CMx x→
R[1:0]= ‘00’ updateno→
1
1
20
CHA0/CMA
CHB0/CMB
conversionn
ofbothCH 0/CMx x
CHA1/CMA
ofbothCH 1x
C[1:0]= ‘01’ CH 1/CMx x→
R[1:0]= ‘11’ updateno→
C[1:0]areignored
R[1:0]= ‘00’ updateno→
C[1:0]areignored
R[1:0]= ‘11’ updateno→
20
1
20
1
CHB0
20
1
C[1:0]=’10’ CHx2/CMx→
R[1:0]=’00’ updateno→
noconversion
readaccessonly
every ndCONVST2
is ignored
every ndCONVST2
is ignored
no conversion
readaccessonly
A
D
B
A
D
A
A
D
B
A
D
A
ofbothCH 0x
M[1:0]= ‘00’ M[1:0]= ‘10’
16-bitdata n - 2 16-bitdatan
16-bitdatan
16-bitdatan+1
conversionn+1
16-bitdata 1n -
conversionn 1-
ADS8363
ADS7263
ADS7223
SBAS523B –OCTOBER 2010–REVISED JANUARY 2011 www.ti.com
Mode II (Half-Clock Mode Only)
The output data consist of a '0', followed by an ADC
indicator ('0' for CHAx or '1' for CHBx), and then 16,
With M0 = '0' and M1 = '1', the ADS8363/7263/7223
14, or 12 bits of conversion result along with any
also operate in manual channel-control mode and
trailing zeroes.
output data on the SDOA pin only while SDOB is set
to high impedance. All other pins function in the same
This mode can be used for fully- or
manner as they do in Mode I.
pseudo-differential inputs. Channel information is
valid in fully-differential mode only if CID = '0' (it
In half-clock mode, because it takes 40 clock cycles
contains correct ADC information while the channel
to output the results from both ADCs (instead of 20
bit is invalid in pseudo-differential mode). Note that
cycles if M1 = '0'), the device requires 2.0ms to
FIFO is not available in this mode.
perform a complete read cycle. If the CONVST signal
is issued every 1.0ms (required for the RD signal) as
Changes to register bits FE, SR, PDE, and CID are
in Mode I, every second pulse is ignored, as shown in
active with the start of the next conversion; this is
Figure 35. CONVST and RD signals must not be
with a delay of one read access.
longer than one clock cycle to ensure proper
The register settings should be updated using every
functionality and avoid corruption of output data.
other RD pulse, aligned either with the one starting
Full-clock mode is not supported in this operational
the conversion or the one to read the conversion
mode.
results of channel B, as shown in Figure 35.
(1) ADS7263/7223 output data with the MSB located as ADS8363 and the last 2/4 bits being '0'.
Figure 35. Mode II Timing
(M0 = '0', M1 = '1', PDE = '0', CID = '0', Pseudo-Differential Example)
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