Datasheet

1
20
CLOCK
CONVST
andRD
SDI
CONVST
andRD
SDOx
(1)
BUSY
16-bitdata 2n -
CHxx
C[1:0]=’00’ CH 0x next→
R[1:0]=’00’ no update→
1
1
20
conversionn 1-
ofbothCHxx
16-bitdatan
CH 0x
16-bitdatan+1
CH 1x
conversionn
ofbothCH 0x
16-bitdatan+2
CH 1x
conversionn+2
ofbothCH 1x
C[1:0]=’11’ CH 1x next→
R[1:0]=’11’ no update→
C[1:0]=’11’ CH 1x next→
R[1:0]=’11’ no update→
C[1:0]=’00’ CH 0x next→
R[1:0]=’00’ no update→
20
1
20
1
16-bitdata 1n -
CHxx
20
1
C[1:0]=’00’ CH 0x next→
R[1:0]=’00’ no update→
conversionn+3
ofbothCH 0x
conversionn+1
ofbothCH 1x
conversion 1n -
ofbothCHxx
16-bitdatan
CH 0x
16-bit 1data n -
CHxx
conversionn
ofbothCH 0x
SDOx
(1)
BUSY
Full-ClockMode
Half-ClockMode
C[1:0]=’00’ CH 0x next→
R[1:0]=’00’ no update→
C[1:0]=’11’ CH 1x next→
R[1:0]=’11’ no update→
SDI
conversionn+1
ofbothCH 1x
ADS8363
ADS7263
ADS7223
www.ti.com SBAS523B –OCTOBER 2010–REVISED JANUARY 2011
Mode I
CONFIG register bits C[1:0]. CS must be brought low
to enable both serial outputs. Data are valid on the
With the M0 and M1 pins both set to '0', the device
falling edge of every 20 clock cycles per conversion.
enters manual channel-control operation and outputs
The first two bits are set to '0'. The subsequent data
data on both SDOA and SDOB, accordingly. The SDI
contain the 16-, 14-, or 12-bit conversion result (the
pin can be used to switch between the channels, as
most significant bit is transferred first), with trailing
explicitly shown in the corresponding timing
zeroes, as shown in Figure 34.
diagrams. A conversion is initiated by bringing
CONVST high.
This mode can be used for fully- or
pseudo-differential inputs; in both cases, channel
With the rising edge of CONVST, the device switches
information bits are '00' if CID = '0'. Note that FIFO is
asynchronously to the external CLOCK from sample
not available in this mode.
to hold mode, and the BUSY output pin goes high
and remains high for the duration of the conversion
cycle. On the falling edge of the second CLOCK
cycle, the device latches in the channel for the next
conversion cycle, depending on the status of
(1) ADS7263/7223 output data with the MSB located as ADS8363 and the last 2/4 bits being '0'.
Figure 34. Mode I Timing
(M0 = '0', M1 = '0', PDE = '0', CID = '1', Fully-Differential Example)
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