Datasheet

ADS8363
ADS7263
ADS7223
SBAS523B –OCTOBER 2010–REVISED JANUARY 2011 www.ti.com
READ DATA INPUT (RD) Note that in full-clock mode, only the first read access
delivers the correct channel information (if CID = '0' in
The RD input is used to control serial data outputs
the CONFIG register), while the following readouts
SDOx. The falling edge of the RD pulse triggers the
contain invalid channel details. The channel
output of the first bit of the output data. When CID =
information is corrected with the next conversion.
'0' this is the analog input channel indicator; when
CID = '1', this is the MSB of the conversion result, or Read access to verify the content of the internal
the 15th bit of the selected register, followed by registers is described in the Register Map section.
output bits that are updated with the rising edge of
the CLOCK in half-clock mode, or falling edge of the
SERIAL DATA OUTPUTS (SDOx)
CLOCK in full-clock mode.
The following sections explain the different modes of
The RD input can be controlled separately or in
operation in detail.
combination with the CONVST input (see Figure 43
The digital output code format of the
for a detailed timing diagram of this case). If RD is
ADS8363/7263/7223 is binary twos complement, as
controlled separately, it can be issued whenever a
shown in Table 13.
conversion process has been finished (that is, after
the falling edge of BUSY). However, in order to
Consider both detailed timing diagrams (Figure 1 and
achieve the maximum data rate, the conversion
Figure 2) shown in the Timing Diagrams section. For
results must be read during an ongoing conversion.
maximum data throughput, the description and
In this case, the RD pulse should not be issued
diagrams given in this data sheet assume that the
between the 16th and 19th clock cycle in half-clock
CONVST and RD pins are tied together; see
mode, or between the 34th and 36th clock cycle in
Figure 43 for timing details in this case. Note that
full-clock mode, after starting the conversion.
these pins can also be controlled independently.
If a read access is repeated without issuing a new
conversion, the result of the last conversion is
presented on the output(s) again. A repeated readout
should only be performed when BUSY is low.
Table 13. Output Data Format
DIFFERENTIAL INPUT VOLTAGE AT CHxxP HEXADECIMAL
DESCRIPTION INPUT VOLTAGE (CHxxN = V
REF
= 2.5V) BINARY CODE CODE
ADS8363: 0111 1111 1111 1111 7FFF
Positive full-scale V
REF
5V ADS7263: 0111 1111 1111 1100 7FFC
ADS7223: 0111 1111 1111 0000 7FF0
Midscale 0V 2.5V 0000 0000 0000 0000 0000
ADS8363: 2.499924V ADS8363: 1111 1111 1111 1111 FFFF
Midscale – 1LSB –V
REF
/resolution ADS7263: 2.499847V ADS7263: 1111 1111 1111 1100 FFFC
ADS7223: 2.499390V ADS7223: 1111 1111 1111 0000 FFF0
Negative full-scale –V
REF
0V 1000 0000 0000 0000 8000
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