Datasheet

1
20
CLOCK
CONVST
RD
CS
SDOx
(1)
BUSY
1
1
20
16bitdatan
CHx0
16bitdatan+1
dataCHx1
conversionn
ofbothCHx0
16bitdatan+2
CHx1
conversionn+2
ofbothCHx1
20
1
20
1
16bitdatan-1
CHxx
C
H
x
20
1
conversionn+3
ofbothCHx0
conversionn+1
ofbothCHx1
16bitdatan+3
CHx0
conversionn+4
bothCHx0
SDI
R[1:0]=’01’ registerupdate→
CE= ‘1’
R[1:0]=’00’ noupdate→
R[1:0]=’11’ noupdate→
R[1:0]=’00’ noupdate→ R[1:0]=’00’ noupdate→
ADS8363
ADS7263
ADS7223
SBAS523B –OCTOBER 2010–REVISED JANUARY 2011 www.ti.com
Bits[3:0] A[3:0]—Register access control.
These bits allow reading of the CONFIG register contents and control the access to the remaining registers of the device.
x000 = Update CONFIG register contents only (default)
0001 = Read CONFIG register content on SDOA with next access (see Figure 30).
x010 = Write to REFDAC1 register with next access (see Figure 30).
0011 = Read REFDAC1 register content on SDOA with next access (see Figure 30).
0100 = Generate software reset of the device.
x101 = Write to REFDAC2 register with next access (see Figure 30).
0110 = Read REFDAC2 register content on SDOA with next access (see Figure 30).
x111 = Update CONFIG register contents only.
1001 = Write to SEQFIFO register with next access (see Figure 30).
1011 = Read SEQFIFO register content on SDOA with next access (see Figure 30).
1100 = Write to REFCM register with next access (see Figure 30).
1110 = Read REFCM register content on SDOA with next access (see Figure 30).
(1) ADS7263/7223 output data with the MSB located as ADS8363 and the last 2/4 bits being '0'.
Figure 31. 2-Bit Counter Feature
(Half-Clock Mode, Manual Channel Control, CID = '0')
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Product Folder Link(s): ADS8363 ADS7263 ADS7223