Datasheet

ADS8363
ADS7263
ADS7223
www.ti.com SBAS523B –OCTOBER 2010–REVISED JANUARY 2011
Configuration (CONFIG) Register
The configuration register selects the input channel, the activation of power-down modes, and the access to the
sequencer/FIFO, reference selection, and reference DAC registers.
Table 7. CONFIG: Configuration Register (default = 0000h)
MSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
C1 C0 R1 R0 PD1 PD0 FE SR FC PDE CID CE A3 A2 A1 A0
Bits[15:14] C[1:0]—Input Channel Selection (ADS8361-compatible).
These bits control the multiplexer input selection depending on the status of the PDE bit.
If PDE = '0' (default), the multiplexer is in fully-differential mode and bits C[1:0] control the input multiplexer in the
following manner:
0x = conversion of analog signals at inputs CHx0P/CHx0N (default).
1x = conversion of analog signals at inputs CHx1P/CHx1N.
If PDE = '1', the multiplexer is in pseudo-differential mode and bits C[1:0] control the input multiplexer in the following
manner:
00 = conversion of analog signal at input CHx0 versus the selected CMx or REFIOx (default).
01 = conversion of analog signal at input CHx1 versus the selected CMx or REFIOx.
10 = conversion of analog signal at input CHx2 versus the selected CMx or REFIOx.
11 = conversion of analog signal at input CHx3 versus the selected CMx or REFIOx.
Bits[13:12] R[1:0]—Configuration register update control.
These bits control the access to the CONFIG register.
00 = If M0 = '0', update of input selection bits C[1:0] only (ADS8361-compatible behavior); if M0 = '1', no action (default).
01 = Update of the entire CONFIG register content enabled.
10 = Reserved for factory test; do not use. Changes may result in false behavior of the device.
11 = If M0 = '0', update of input selection bits C[1:0] only (ADS8361-compatible behavior); if M0 = '1', no action.
Bits[11:10] PD[1:0]—Power-down control.
These bits control the different power-down modes of the device.
00 = Normal operation (default).
01 = Device is in power-down mode (see the Power-Down Modes and Reset section for details).
10 = Device is in sleep power-down mode (see the Power-Down Modes and Reset section for details).
11 = Device is in Auto-sleep power-down mode (see the Power-Down Modes and Reset section for details).
Bit 9 FE—FIFO enable control.
0 = The internal FIFO is disabled (default).
1 = The internal FIFO is enabled. The depth of the FIFO is controlled by SEQFIFO register bits FD[1:0].
Bit 8 SR—Special read mode control.
0 = Special read mode is disabled (default).
1 = Special read mode is enabled; see Figure 36 and Figure 39 for details.
Bit 7 FC—Full clock mode operation control.
0 = Full-clock mode operation is disabled (default); see Figure 1 for details.
1 = Full-clock mode operation is enabled; see Figure 2 for details.
Bit 6 PDE—Pseudo-differential mode operation enable.
0 = 2 x 2 fully-differential operation (default).
1 = 4 x 2 pseudo-differential operation.
Bit 5 CID—Channel information disable.
0 = The channel information followed by conversion results or register contents are present on SDOx (default).
1 = Conversion data or register content is present on SDOx immediately after the falling edge of RD.
Bit 4 CE—2-bit counter enable (see Figure 31).
0: The internal counter is disabled (default).
1: The counter value is available prior to the conversion result on SDOx (active only if CID = '0').
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