Datasheet

Full-Clock Mode
Half-Clock Mode
1
20
CLOCK
CONVST
and RD
SDI
CONVST
and RD
SDOx
(1)
conversion result
n 1-
R[1:0]=’01’ update enabled
→
A[3:0]=’1001’ SEQFIFO update→
1
1
20
conversion result
n + 1
conversion result
n + 3
R[1:0]=’01’ update enabled
→
A[3:0]=’1011’ read SEQFIFO→
SDI ignored because a register
read access is ongoing
20
1
20
1
20
1
conversion result
n + 1
conversion result
n
SDOx
(1)
SDI
conversion n conversion n + 2 conversion n + 3 conversion n + 4
SEQFIFO
register value
conversion n conversion n + 1
R[1:0]=’01’ update enabled
→
A[3:0]=’1001’ SEQFIFO update→
SEQFIFO register
setting value
conversion result
n
SEQFIFO register
setting value
conversion n + 1
CID = ‘1’
ADS8363
ADS7263
ADS7223
SBAS523B –OCTOBER 2010–REVISED JANUARY 2011 www.ti.com
REGISTERS
Register Map
ADS8363/7263/7223 operation is controlled through a set of registers described in the following sections. Table 6
shows the register map. The contents of these 16-bit registers can be set using the serial data input (SDI) pin,
which is coupled to RD and clocked into the device on each falling edge of CLOCK. All data must be transferred
MSB first. All register updates become active with the rising edge of CLOCK after completing the 16-clock-cycle
write access operation.
Table 6. Register Map
BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT
REGISTER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CONFIG C1 C0 R1 R0 PD1 PD0 FE SR FC PDE CID CE A3 A2 A1 A0
REFDAC1 0 0 0 0 0 RPD D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
REFDAC2 0 0 0 0 0 RPD D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SEQFIFO S1 S0 SL1 SL0 C11 C10 C21 C20 C31 C30 C41 C40 SP1 SP0 FD1 FD0
REFCM CMB3 CMB2 CMB1 CMB0 CMA3 CMA2 CMA1 CMA0 RB3 RB2 RB1 RB0 RA3 RA2 RA1 RA0
To update the CONFIG register, a single write access is required. To update the contents of all the other
registers, a write access to the control register with the appropriate register address (bits A[3:0]), followed by a
write access to the actual register is required (refer to Figure 30). It is possible to update the CONFIG register
contents while issuing a register read out access with a single register write access. For example, it is possible to
change the mode of the device to full-clock mode while activating the REFDAC1 register read access; because
full-clock mode is active upon the 16th clock cycle of the CONFIG register update, the REFDAC1 data are then
presented according to the full-clock mode timing.
To verify the register contents, a read access may be issued using CONFIG register bits A[3:0]. Such access is
described in the Programming the Reference DAC section, based on an example of verifying the reference DAC
register settings. The register contents are always available on SDOA with the next read command. For example,
if the FIFO is used, the register contents are presented after completion of the FIFO read access (see Table 10
for more details). In both cases, a complete read or write access requires a total of 40 clock cycles, during which
a new access to the CONFIG register is not allowed.
(1) ADS7263/7223 output data with the MSB located as ADS8363 and the last 2/4 bits being '0'.
Figure 30. Updating Internal Register Settings
(Example: Half-Clock Mode, CID = '1')
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